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modules/nrfx/hal/nrf_mpu.h
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185
modules/nrfx/hal/nrf_mpu.h
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/**
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* Copyright (c) 2019 - 2020, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRF_MPU_H__
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#define NRF_MPU_H__
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#include <nrfx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @defgroup nrf_mpu_hal MPU HAL
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* @{
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* @ingroup nrf_mpu
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* @brief Hardware access layer for managing the Memory Protection Unit (MPU) peripheral.
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*/
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/**
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* @brief Macro for getting MPU region configuration mask for the specified peripheral.
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*
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* @param[in] base_addr Peripheral base address.
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*
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* @return MPU configuration mask for the specified peripheral.
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*/
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#define NRF_MPU_PERIPHERAL_MASK_GET(base_addr) (1UL << NRFX_PERIPHERAL_ID_GET(base_addr))
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/**
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* @brief Function for setting the size of the RAM region 0.
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*
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* When memory protection is enabled, the Memory Protection Unit enforces
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* runtime protection and readback protection of resources classified as region 0.
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* See the product specification for more information.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] size Size of the RAM region 0, in bytes. Must be word-aligned.
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*/
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__STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size);
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/**
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* @brief Function for configuring specified peripherals in the memory region 0.
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*
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* When the memory protection is enabled, the Memory Protection Unit enforces
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* runtime protection and readback protection of resources classified as region 0.
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* See the product specification for more information.
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*
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* After reset, all peripherals are configured as *not* assigned to region 0.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] peripheral_mask Mask that specifies peripherals to be configured in the memory region 0.
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* Compose this mask using @ref NRF_MPU_PERIPHERAL_MASK_GET macro.
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*/
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__STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
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uint32_t peripheral_mask);
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/**
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* @brief Function for getting the bitmask that specifies peripherals configured in the memory region 0.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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*
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* @return Bitmask representing peripherals configured in region 0.
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*/
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__STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg);
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/**
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* @brief Function for enabling protection for specified non-volatile memory blocks.
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*
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* Blocks are arranged into groups of 32 blocks each. Each block size is 4 kB.
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* Any attempt to write or erase a protected block will result in hard fault.
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* The memory block protection can be disabled only by resetting the device.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] group_idx Non-volatile memory group containing memory blocks to protect.
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* @param[in] block_mask Non-volatile memory blocks to protect. Each bit in bitmask represents
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* one memory block in the specified group.
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*/
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__STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
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uint8_t group_idx,
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uint32_t block_mask);
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/**
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* @brief Function for setting the non-volatile memory (NVM) protection during debug.
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*
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* NVM protection during debug is disabled by default.
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*
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* @param[in] p_reg Pointer to the structure of registers of the peripheral.
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* @param[in] enable True if NVM protection during debug is to be enabled.
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* False if otherwise.
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*/
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__STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
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bool enable);
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#ifndef SUPPRESS_INLINE_IMPLEMENTATION
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__STATIC_INLINE void nrf_mpu_region0_ram_size_set(NRF_MPU_Type * p_reg, uint32_t size)
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{
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NRFX_ASSERT(nrfx_is_word_aligned((const void *)size));
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p_reg->RLENR0 = size;
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}
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__STATIC_INLINE void nrf_mpu_region0_peripherals_set(NRF_MPU_Type * p_reg,
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uint32_t peripheral_mask)
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{
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p_reg->PERR0 = peripheral_mask;
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}
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__STATIC_INLINE uint32_t nrf_mpu_region0_peripherals_get(NRF_MPU_Type const * p_reg)
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{
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return p_reg->PERR0;
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}
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__STATIC_INLINE void nrf_mpu_nvm_blocks_protection_enable(NRF_MPU_Type * p_reg,
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uint8_t group_idx,
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uint32_t block_mask)
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{
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switch (group_idx)
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{
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case 0:
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p_reg->PROTENSET0 = block_mask;
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break;
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case 1:
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p_reg->PROTENSET1 = block_mask;
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break;
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default:
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NRFX_ASSERT(false);
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break;
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}
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}
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__STATIC_INLINE void nrf_mpu_nvm_protection_in_debug_set(NRF_MPU_Type * p_reg,
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bool enable)
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{
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p_reg->DISABLEINDEBUG =
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(enable ? 0 : MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk);
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}
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#endif // SUPPRESS_INLINE_IMPLEMENTATION
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif // NRF_MPU_H__
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