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xiaozhengsheng
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modules/nrfx/soc/nrfx_atomic_internal.h
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335
modules/nrfx/soc/nrfx_atomic_internal.h
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/**
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* Copyright (c) 2016 - 2020, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRFX_ATOMIC_INTERNAL_H__
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#define NRFX_ATOMIC_INTERNAL_H__
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#include <nrfx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Only Cortex-M cores > 3 support LDREX/STREX instructions. */
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#if ((__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)) == 0
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#error "Unsupported core version"
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#endif
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#if defined ( __CC_ARM )
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static __asm uint32_t nrfx_atomic_internal_mov(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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/* The base standard specifies that arguments are passed in the core registers
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* r0-r3 and on the stack. Registers r4 and r5 must be saved on the stack.
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* Only even number of register pushes are allowed. This is a requirement
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* of the Procedure Call Standard for the ARM Architecture [AAPCS].
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*/
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push {r4, r5}
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mov r4, r0
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loop_mov
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ldrex r0, [r4]
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mov r5, r1
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_mov
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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static __asm uint32_t nrfx_atomic_internal_orr(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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push {r4, r5}
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mov r4, r0
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loop_orr
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ldrex r0, [r4]
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orr r5, r0, r1
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_orr
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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static __asm uint32_t nrfx_atomic_internal_and(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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push {r4, r5}
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mov r4, r0
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loop_and
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ldrex r0, [r4]
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and r5, r0, r1
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_and
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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static __asm uint32_t nrfx_atomic_internal_eor(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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push {r4, r5}
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mov r4, r0
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loop_eor
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ldrex r0, [r4]
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eor r5, r0, r1
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_eor
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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static __asm uint32_t nrfx_atomic_internal_add(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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push {r4, r5}
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mov r4, r0
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loop_add
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ldrex r0, [r4]
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add r5, r0, r1
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_add
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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static __asm uint32_t nrfx_atomic_internal_sub(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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push {r4, r5}
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mov r4, r0
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loop_sub
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ldrex r0, [r4]
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sub r5, r0, r1
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_sub
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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static __asm bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data,
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uint32_t * p_expected,
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uint32_t value)
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{
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#define RET_REG r0
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#define P_EXPC r1
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#define VALUE r2
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#define STR_RES r3
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#define P_DATA r4
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#define EXPC_VAL r5
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#define ACT_VAL r6
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push {r4-r6}
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mov P_DATA, r0
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mov RET_REG, #0
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loop_cmp_exch
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ldrex ACT_VAL, [P_DATA]
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ldr EXPC_VAL, [P_EXPC]
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cmp ACT_VAL, EXPC_VAL
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ittee eq
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strexeq STR_RES, VALUE, [P_DATA]
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moveq RET_REG, #1
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strexne STR_RES, ACT_VAL, [P_DATA]
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strne ACT_VAL, [P_EXPC]
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cmp STR_RES, #0
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itt ne
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movne RET_REG, #0
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bne loop_cmp_exch
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pop {r4-r6}
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bx lr
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#undef RET_REG
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#undef P_EXPC
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#undef VALUE
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#undef STR_RES
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#undef P_DATA
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#undef EXPC_VAL
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#undef ACT_VAL
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}
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static __asm uint32_t nrfx_atomic_internal_sub_hs(nrfx_atomic_u32_t * p_ptr,
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uint32_t value,
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uint32_t * p_new)
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{
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push {r4, r5}
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mov r4, r0
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loop_sub_ge
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ldrex r0, [r4]
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cmp r0, r1
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ite hs
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subhs r5, r0, r1
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movlo r5, r0
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strex r3, r5, [r4]
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cmp r3, #0
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bne loop_sub_ge
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str r5, [r2]
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pop {r4, r5}
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bx lr
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}
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#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \
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old_val = nrfx_atomic_internal_##asm_op(ptr, value, &new_val)
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#elif defined ( __ICCARM__ ) || defined ( __GNUC__ )
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/**
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* @brief Atomic operation generic macro.
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*
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* @param[in] asm_op Operation: mov, orr, and, eor, add, sub.
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* @param[out] old_val Atomic object output (uint32_t); value before operation.
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* @param[out] new_val Atomic object output (uint32_t); value after operation.
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* @param[in] value Atomic operation operand.
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*/
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#define NRFX_ATOMIC_OP(asm_op, old_val, new_val, ptr, value) \
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{ \
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uint32_t tmp_reg; \
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__ASM volatile( \
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"1: ldrex %["#old_val"], [%["#ptr"]]\n" \
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NRFX_ATOMIC_OP_##asm_op(new_val, old_val, value) \
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" strex %[tmp_reg], %["#new_val"], [%["#ptr"]]\n" \
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" teq %[tmp_reg], #0\n" \
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" bne.n 1b" \
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: \
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[old_val] "=&r" (old_val), \
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[new_val] "=&r" (new_val), \
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[tmp_reg] "=&r" (tmp_reg) \
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: \
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[ptr] "r" (ptr), \
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[value] "r" (value) \
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: "cc"); \
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(void)tmp_reg; \
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}
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#define NRFX_ATOMIC_OP_mov(new_val, old_val, value) "mov %["#new_val"], %["#value"]\n"
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#define NRFX_ATOMIC_OP_orr(new_val, old_val, value) "orr %["#new_val"], %["#old_val"], %["#value"]\n"
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#define NRFX_ATOMIC_OP_and(new_val, old_val, value) "and %["#new_val"], %["#old_val"], %["#value"]\n"
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#define NRFX_ATOMIC_OP_eor(new_val, old_val, value) "eor %["#new_val"], %["#old_val"], %["#value"]\n"
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#define NRFX_ATOMIC_OP_add(new_val, old_val, value) "add %["#new_val"], %["#old_val"], %["#value"]\n"
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#define NRFX_ATOMIC_OP_sub(new_val, old_val, value) "sub %["#new_val"], %["#old_val"], %["#value"]\n"
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#define NRFX_ATOMIC_OP_sub_hs(new_val, old_val, value) \
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"cmp %["#old_val"], %["#value"]\n " \
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"ite hs\n" \
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"subhs %["#new_val"], %["#old_val"], %["#value"]\n" \
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"movlo %["#new_val"], %["#old_val"]\n"
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static inline bool nrfx_atomic_internal_cmp_exch(nrfx_atomic_u32_t * p_data,
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uint32_t * p_expected,
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uint32_t value)
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{
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bool res = false;
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/* Temporary register used in the inline asm code for getting the result
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* of the strex* operations (no need to initialize it).
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*/
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uint32_t tmp_reg;
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uint32_t act_val = 0;
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uint32_t exp_val = 0;
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__ASM volatile(
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"1: ldrex %[act_val], [%[ptr]]\n"
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" ldr %[exp_val], [%[expc]]\n"
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" cmp %[act_val], %[exp_val]\n"
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" ittee eq\n"
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" strexeq %[tmp_reg], %[value], [%[ptr]]\n"
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" moveq %[res], #1\n"
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" strexne %[tmp_reg], %[act_val], [%[ptr]]\n"
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" strne %[act_val], [%[expc]]\n"
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" cmp %[tmp_reg], #0\n"
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" itt ne\n"
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" movne %[res], #0\n"
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" bne.n 1b"
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:
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[res] "=&r" (res),
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[exp_val] "=&r" (exp_val),
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[act_val] "=&r" (act_val),
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[tmp_reg] "=&r" (tmp_reg)
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:
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"0" (res),
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"1" (exp_val),
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"2" (act_val),
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[expc] "r" (p_expected),
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[ptr] "r" (p_data),
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[value] "r" (value)
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: "cc");
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(void)tmp_reg;
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return res;
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}
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#else
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#error "Unsupported compiler"
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif // NRFX_ATOMIC_INTERNAL_H__
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