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modules/nrfx/soc/nrfx_coredep.h
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modules/nrfx/soc/nrfx_coredep.h
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/**
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* Copyright (c) 2018 - 2020, Nordic Semiconductor ASA
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic
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* Semiconductor ASA integrated circuit in a product or a software update for
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* such product, must reproduce the above copyright notice, this list of
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* conditions and the following disclaimer in the documentation and/or other
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* materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef NRFX_COREDEP_H__
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#define NRFX_COREDEP_H__
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/**
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* @defgroup nrfx_coredep Core-dependent functionality
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* @{
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* @ingroup nrfx
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* @brief Module containing functions with core-dependent implementation, like delay.
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*/
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#if defined(__NRFX_DOXYGEN__)
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/** @brief Core frequency (in MHz). */
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#define NRFX_DELAY_CPU_FREQ_MHZ
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/** @brief Availability of Data Watchpoint and Trace (DWT) unit in the given SoC. */
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#define NRFX_DELAY_DWT_PRESENT
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/**
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* @brief Number of cycles consumed by one iteration of the internal loop
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* in the function @ref nrfx_coredep_delay_us.
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*
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* This value can be specified externally (for example, when the SoC is emulated).
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*/
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#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES
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#elif defined(NRF51)
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#define NRFX_DELAY_CPU_FREQ_MHZ 16
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#define NRFX_DELAY_DWT_PRESENT 0
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#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA)
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#define NRFX_DELAY_CPU_FREQ_MHZ 64
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#define NRFX_DELAY_DWT_PRESENT 0
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#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
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defined(NRF52833_XXAA) || defined(NRF52840_XXAA) || \
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defined(NRF9160_XXAA)
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#define NRFX_DELAY_CPU_FREQ_MHZ 64
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#define NRFX_DELAY_DWT_PRESENT 1
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#else
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#error "Unknown device."
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#endif
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/**
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* @brief Function for delaying execution for a number of microseconds.
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*
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* The value of @p time_us is multiplied by the frequency in MHz. Therefore, the delay is limited to
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* maximum uint32_t capacity divided by frequency. For example:
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* - For SoCs working at 64MHz: 0xFFFFFFFF/64 = 0x03FFFFFF (67108863 microseconds)
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* - For SoCs working at 16MHz: 0xFFFFFFFF/16 = 0x0FFFFFFF (268435455 microseconds)
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*
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* @sa NRFX_COREDEP_DELAY_US_LOOP_CYCLES
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*
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* @param time_us Number of microseconds to wait.
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*/
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__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us);
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/** @} */
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#ifndef SUPPRESS_INLINE_IMPLEMENTATION
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#if NRFX_CHECK(NRFX_DELAY_DWT_BASED)
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#if !NRFX_DELAY_DWT_PRESENT
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#error "DWT unit not present in the SoC that is used."
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#endif
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__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
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{
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if (time_us == 0)
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{
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return;
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}
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uint32_t time_cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
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// Save the current state of the DEMCR register to be able to restore it before exiting
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// this function. Enable the trace and debug blocks (including DWT).
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uint32_t core_debug = CoreDebug->DEMCR;
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CoreDebug->DEMCR = core_debug | CoreDebug_DEMCR_TRCENA_Msk;
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// Save the current state of the CTRL register in the DWT block. Make sure
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// that the cycle counter is enabled.
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uint32_t dwt_ctrl = DWT->CTRL;
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DWT->CTRL = dwt_ctrl | DWT_CTRL_CYCCNTENA_Msk;
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// Store start value of the cycle counter.
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uint32_t cyccnt_initial = DWT->CYCCNT;
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// Delay required time.
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while ((DWT->CYCCNT - cyccnt_initial) < time_cycles)
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{}
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// Restore preserved registers.
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DWT->CTRL = dwt_ctrl;
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CoreDebug->DEMCR = core_debug;
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}
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#else // NRFX_CHECK(NRFX_DELAY_DWT_BASED)
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__STATIC_INLINE void nrfx_coredep_delay_us(uint32_t time_us)
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{
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if (time_us == 0)
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{
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return;
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}
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// Allow overriding the number of cycles per loop iteration, in case it is
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// needed to adjust this number externally (for example, when the SoC is
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// emulated).
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#ifndef NRFX_COREDEP_DELAY_US_LOOP_CYCLES
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#if defined(NRF51)
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// The loop takes 4 cycles: 1 for SUBS, 3 for BHI.
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#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 4
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#elif defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52820_XXAA)
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// The loop takes 7 cycles: 1 for SUBS, 2 for BHI, 2 wait states
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// for each instruction.
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#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 7
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#else
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// The loop takes 3 cycles: 1 for SUBS, 2 for BHI.
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#define NRFX_COREDEP_DELAY_US_LOOP_CYCLES 3
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#endif
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#endif // NRFX_COREDEP_DELAY_US_LOOP_CYCLES
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// Align the machine code, so that it can be cached properly and no extra
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// wait states appear.
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__ALIGN(16)
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static const uint16_t delay_machine_code[] = {
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0x3800 + NRFX_COREDEP_DELAY_US_LOOP_CYCLES, // SUBS r0, #loop_cycles
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0xd8fd, // BHI .-2
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0x4770 // BX LR
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};
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typedef void (* delay_func_t)(uint32_t);
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const delay_func_t delay_cycles =
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// Set LSB to 1 to execute the code in the Thumb mode.
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(delay_func_t)((((uint32_t)delay_machine_code) | 1));
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uint32_t cycles = time_us * NRFX_DELAY_CPU_FREQ_MHZ;
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delay_cycles(cycles);
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}
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#endif // !NRFX_CHECK(NRFX_DELAY_DWT_BASED_DELAY)
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#endif // SUPPRESS_INLINE_IMPLEMENTATION
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#endif // NRFX_COREDEP_H__
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