ZNKT-ST-M/OBJ/stm32f4xx_exti.o

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..\\FWLIB\\src\\stm32f4xx_exti.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER__asm___16_stm32f4xx_exti_c_28b3b60e____REV16H0







..\\CORE\\core_cmInstr.h
<03>





..\\FWLIB\\src\\stm32f4xx_exti.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: armasm [4d35ec]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER__asm___16_stm32f4xx_exti_c_28b3b60e____REVSHH0







..\\CORE\\core_cmInstr.h
<03>



`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+
|

	
<07><07><07><07><07><07><07><07><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+|

	
<08><08><08><08><08><08><08><08><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+|

	
<08><08><08><08><08><08><08><08><08><08><08><08><08><08><08><08>`<00><><EFBFBD><EFBFBD>armcc+|

	
<08><08><08><08><08><08><08><08><08><08><08><08><08><08><08><08>d<00><00><00><00><00><00><00><00><00><00><00>
..\FWLIB\src\stm32f4xx_exti.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER<00>..\FWLIB\src\stm32f4xx_exti.cComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
?<3F>

mEXTI_DeInit
<00>?<3F>
}EXTI_Init
<00>ziEXTI_InitStruct<10>=
ZtmpY
*
?<3F>
<01>
EXTI_StructInit
<01><00>fiEXTI_InitStruct<10>
?<3F>
<01>
EXTI_GenerateSWInterrupt
<01><00>RiEXTI_LineY

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<01>
EXTI_GetFlagStatus
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<00>^__resultJ
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<01>
EXTI_ClearFlag
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<00>><3E>
<01>
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<00>^__result]
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XbitstatusJ
P?<3F>
<01>EXTI_ClearITPendingBit
<01>
iEXTI_LineY
<00>@4






..\FWLIB\src\stm32f4xx_exti.c


4





..\FWLIB\src\stm32f4xx_exti.c<03>

 ,-"842;*
!


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	'





<01>
}<00><><00><00>}<00><00>}<00><00>}<00><00>}<00><00>}<00>}}<00>

P<00><00>
P<><00>
Q<00><00>
P<00><00>
P<><00>
Q<00><00>
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P<00>
Q<00>
P
__DATE__ "Jan 13 2025"
__TIME__ "13:02:17"
__STDC__ 1
__STDC_VERSION__ 199901L
__STDC_HOSTED__ 1
__STDC_ISO_10646__ 200607
__EDG__ 1
__EDG_VERSION__ 407
__EDG_SIZE_TYPE__ unsigned int
__EDG_PTRDIFF_TYPE__ int
__sizeof_int 4
__sizeof_long 4
__sizeof_ptr 4
__ARMCC_VERSION 5060750
__TARGET_CPU_CORTEX_M4_FP_SP 1
__TARGET_FPU_VFPV4_SP_D16 1
__UVISION_VERSION 529
STM32F407xx 1
STM32F40_41xxx 1
USE_STDPERIPH_DRIVER 1
__CC_ARM 1
__arm 1
__arm__ 1
__TARGET_ARCH_7E_M 1
__TARGET_ARCH_ARM 0
__TARGET_ARCH_THUMB 4
__TARGET_ARCH_A64 0
__TARGET_ARCH_AARCH32 1
__TARGET_PROFILE_M 1
__TARGET_FEATURE_HALFWORD 1
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__TARGET_FEATURE_DSPMUL 1
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__TARGET_FEATURE_DIVIDE 1
__TARGET_FEATURE_UNALIGNED 1
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__TARGET_FEATURE_DMB 1
__TARGET_FPU_VFPV4 1
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__TARGET_FEATURE_EXTENSION_REGISTER_COUNT 16
__APCS_INTERWORK 1
__FP_FAST_FMAF 1
__thumb 1
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__t32__ 1
__OPTIMISE_SPACE 1
__OPTIMISE_LEVEL 0
<00><00><00>EXTI_DeInit<00>EXTI_Init.
EXTI_StructInitm
EXTI_GenerateSWInterrupt<00>
EXTI_GetFlagStatusEXTI_ClearFlagNEXTI_GetITStatus<00>EXTI_ClearITPendingBit


%

.




__stdint_h 
__ARMCLIB_VERSION 5060037
__INT64 __int64
__INT64_C_SUFFIX__ ll
__PASTE2(x,y) x ## y
__PASTE(x,y) __PASTE2(x, y)
__INT64_C(x) __ESCAPE__(__PASTE(x, __INT64_C_SUFFIX__))
__UINT64_C(x) __ESCAPE__(__PASTE(x ## u, __INT64_C_SUFFIX__))
__LONGLONG long long
#__STDINT_DECLS %__CLIBNS
,__CLIBNS 
sINT8_MIN -128
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vINT64_MIN __INT64_C(~0x7fffffffffffffff)
yINT8_MAX 127
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{INT32_MAX 2147483647
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<01>
UINT16_MAX 65535
<01>
UINT32_MAX 4294967295u
<01>
UINT64_MAX __UINT64_C(18446744073709551615)
<01>
INT_LEAST8_MIN -128
<01>
INT_LEAST16_MIN -32768
<01>
INT_LEAST32_MIN (~0x7fffffff)
<01>
INT_LEAST64_MIN __INT64_C(~0x7fffffffffffffff)
<01>
INT_LEAST8_MAX 127
<01>
INT_LEAST16_MAX 32767
<01>
INT_LEAST32_MAX 2147483647
<01>
INT_LEAST64_MAX __INT64_C(9223372036854775807)
<01>
UINT_LEAST8_MAX 255
<01>
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<01>
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<01>
UINT_LEAST64_MAX __UINT64_C(18446744073709551615)
<01>
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<01>
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<01>
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<01>
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<01>
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<01>
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<01>
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<01>
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<01>
UINT_FAST64_MAX __UINT64_C(18446744073709551615)
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<01>
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<01>
INTMAX_MIN __ESCAPE__(~0x7fffffffffffffffll)
<01>
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<01>
PTRDIFF_MIN INT32_MIN
<01>
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<01>
SIG_ATOMIC_MIN (~0x7fffffff)
<01>
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<01>
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<01>UINTMAX_C(x) __ESCAPE__(x ## ull)<02>__INT64<02>__LONGLONGPD






C:\Keil_v5\ARM\ARMCC\Bin\..\include\stdint.h



..\CORE\core_cmInstr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER


'__CORE_CMFUNC_H 
<01>
__enable_fault_irq __enable_fiq
<01>
__disable_fault_irq __disable_fiq8-






..\CORE\core_cmFunc.h


<01>
..\CORE\core_cmFunc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER;<3B>

@__get_CONTROLY
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g__get_APSRY
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Y__regAPSRY

P;<3B>
t__get_xPSRY
a__resultY

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P;<3B>
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<01>
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P;<3B>
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<01>
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P;<3B>
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P;<3B>
<01>
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P;<3B>
<01>
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P<<3C>
<01>__set_FAULTMASK$Y
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P;<3B>	
<01>__get_FPSCRY
a__resultY

Y__regfpscrY

P<<3C>	
<01>__set_FPSCR$Y
fpscrY__regfpscrY

P
!"#

+__CORE_CM4_SIMD_H 
=__SADD8 __sadd8
>__QADD8 __qadd8
?__SHADD8 __shadd8
@__UADD8 __uadd8
A__UQADD8 __uqadd8
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J__QADD16 __qadd16
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o__SMUSD __smusd
p__SMUSDX __smusdx
q__SMLSD __smlsd
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t__SMLSLDX __smlsldx
u__SEL __sel
v__QADD __qadd
w__QSUB __qsub
y__PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|__PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
__SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32) ) >> 32))8/






..\CORE\core_cm4_simd.h


<01>
..\CORE\core_cm4_simd.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
%&'(

/__CORE_CM4_H_GENERIC 
G__CM4_CMSIS_VERSION_MAIN (0x03)
H__CM4_CMSIS_VERSION_SUB (0x20)
I__CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB )
L__CORTEX_M (0x04)
P__ASM __asm
Q__INLINE __inline
R__STATIC_INLINE static __inline
n__FPU_USED 1<03>
<03>
<03>
<03>

<01>
__CORE_CM4_H_DEPENDANT 
<01>
__I volatile const
<01>
__O volatile
<01>
__IO volatile
<01>NVIC_STIR_INTID_Pos 0
<01>NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos)
<01>SCB_CPUID_IMPLEMENTER_Pos 24
<01>SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
<01>SCB_CPUID_VARIANT_Pos 20
<01>SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
<01>SCB_CPUID_ARCHITECTURE_Pos 16
<01>SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
<01>SCB_CPUID_PARTNO_Pos 4
<01>SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
<01>SCB_CPUID_REVISION_Pos 0
<01>SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos)
<01>SCB_ICSR_NMIPENDSET_Pos 31
<01>SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
<01>SCB_ICSR_PENDSVSET_Pos 28
<01>SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
<01>SCB_ICSR_PENDSVCLR_Pos 27
<01>SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
<01>SCB_ICSR_PENDSTSET_Pos 26
<01>SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
<01>SCB_ICSR_PENDSTCLR_Pos 25
<01>SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
<01>SCB_ICSR_ISRPREEMPT_Pos 23
<01>SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
<01>SCB_ICSR_ISRPENDING_Pos 22
<01>SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
<01>SCB_ICSR_VECTPENDING_Pos 12
<01>SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
<01>SCB_ICSR_RETTOBASE_Pos 11
<01>SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
<01>SCB_ICSR_VECTACTIVE_Pos 0
<01>SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
<01>SCB_VTOR_TBLOFF_Pos 7
<01>SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
<01>SCB_AIRCR_VECTKEY_Pos 16
<01>SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
<01>SCB_AIRCR_VECTKEYSTAT_Pos 16
<01>SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
<01>SCB_AIRCR_ENDIANESS_Pos 15
<01>SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
<01>SCB_AIRCR_PRIGROUP_Pos 8
<01>SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
<01>SCB_AIRCR_SYSRESETREQ_Pos 2
<01>SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
<01>SCB_AIRCR_VECTCLRACTIVE_Pos 1
<01>SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
<01>SCB_AIRCR_VECTRESET_Pos 0
<01>SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos)
<01>SCB_SCR_SEVONPEND_Pos 4
<01>SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
<01>SCB_SCR_SLEEPDEEP_Pos 2
<01>SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
<01>SCB_SCR_SLEEPONEXIT_Pos 1
<01>SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
<01>SCB_CCR_STKALIGN_Pos 9
<01>SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
<01>SCB_CCR_BFHFNMIGN_Pos 8
<01>SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
<01>SCB_CCR_DIV_0_TRP_Pos 4
<01>SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
<01>SCB_CCR_UNALIGN_TRP_Pos 3
<01>SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
<01>SCB_CCR_USERSETMPEND_Pos 1
<01>SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
<01>SCB_CCR_NONBASETHRDENA_Pos 0
<01>SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos)
<01>SCB_SHCSR_USGFAULTENA_Pos 18
<01>SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
<01>SCB_SHCSR_BUSFAULTENA_Pos 17
<01>SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
<01>SCB_SHCSR_MEMFAULTENA_Pos 16
<01>SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
<01>SCB_SHCSR_SVCALLPENDED_Pos 15
<01>SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
<01>SCB_SHCSR_BUSFAULTPENDED_Pos 14
<01>SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
<01>SCB_SHCSR_MEMFAULTPENDED_Pos 13
<01>SCB_SHCSR_MEMFAULTPENDED_Msk (1U
CoreDebug_DHCSR_DBGKEY_Pos 16
<01>
CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
<01>
CoreDebug_DHCSR_S_RESET_ST_Pos 25
<01>
CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
<01>
CoreDebug_DHCSR_S_RETIRE_ST_Pos 24
<01>
CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
<01>
CoreDebug_DHCSR_S_LOCKUP_Pos 19
<01>
CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
<01>
CoreDebug_DHCSR_S_SLEEP_Pos 18
<01>
CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
<01>
CoreDebug_DHCSR_S_HALT_Pos 17
<01>
CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
<01>
CoreDebug_DHCSR_S_REGRDY_Pos 16
<01>
CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
<01>
CoreDebug_DHCSR_C_SNAPSTALL_Pos 5
<01>
CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
<01>
CoreDebug_DHCSR_C_MASKINTS_Pos 3
<01>
CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
<01>
CoreDebug_DHCSR_C_STEP_Pos 2
<01>
CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
<01>
CoreDebug_DHCSR_C_HALT_Pos 1
<01>
CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
<01>
CoreDebug_DHCSR_C_DEBUGEN_Pos 0
<01>
CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
<01>
CoreDebug_DCRSR_REGWnR_Pos 16
<01>
CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
<01>
CoreDebug_DCRSR_REGSEL_Pos 0
<01>
CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
<01>
CoreDebug_DEMCR_TRCENA_Pos 24
<01>
CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
<01>
CoreDebug_DEMCR_MON_REQ_Pos 19
<01>
CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
<01>
CoreDebug_DEMCR_MON_STEP_Pos 18
<01>
CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
<01>
CoreDebug_DEMCR_MON_PEND_Pos 17
<01>
CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
<01>
CoreDebug_DEMCR_MON_EN_Pos 16
<01>
CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
<01>
CoreDebug_DEMCR_VC_HARDERR_Pos 10
<01>
CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
<01>
CoreDebug_DEMCR_VC_INTERR_Pos 9
<01>
CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
<01>
CoreDebug_DEMCR_VC_BUSERR_Pos 8
<01>
CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
<01>
CoreDebug_DEMCR_VC_STATERR_Pos 7
<01>
CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
<01>
CoreDebug_DEMCR_VC_CHKERR_Pos 6
<01>
CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
<01>
CoreDebug_DEMCR_VC_NOCPERR_Pos 5
<01>
CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
<01>
CoreDebug_DEMCR_VC_MMERR_Pos 4
<01>
CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
<01>
CoreDebug_DEMCR_VC_CORERESET_Pos 0
<01>
CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)
<01>
SCS_BASE (0xE000E000UL)
<01>
ITM_BASE (0xE0000000UL)
<01>
DWT_BASE (0xE0001000UL)
<01>
TPI_BASE (0xE0040000UL)
<01>
CoreDebug_BASE (0xE000EDF0UL)
<01>
SysTick_BASE (SCS_BASE + 0x0010UL)
<01>
NVIC_BASE (SCS_BASE + 0x0100UL)
<01>
SCB_BASE (SCS_BASE + 0x0D00UL)
<01>
SCnSCB ((SCnSCB_Type *) SCS_BASE )
<01>
SCB ((SCB_Type *) SCB_BASE )
<01>
SysTick ((SysTick_Type *) SysTick_BASE )
<01>
NVIC ((NVIC_Type *) NVIC_BASE )
<01>
ITM ((ITM_Type *) ITM_BASE )
<01>
DWT ((DWT_Type *) DWT_BASE )
<01>
TPI ((TPI_Type *) TPI_BASE )
<01>
CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
<01>
MPU_BASE (SCS_BASE + 0x0D90UL)
<01>
MPU ((MPU_Type *) MPU_BASE )
<01>
FPU_BASE (SCS_BASE + 0x0F30UL)
<01>
FPU ((FPU_Type *) FPU_BASE )
<01>
ITM_RXBUFFER_EMPTY 0x5AA55AA5<00><00>






..\CORE\C:\Keil_v5\ARM\ARMCC\Bin\..\include\core_cm4.h
stdint.hcore_cmInstr.h
core_cmFunc.h
core_cm4_simd.h


<01>
..\CORE\core_cm4.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>!_reserved0Y
#!GEY
#!_reserved1Y
#!QY
#
!VY
#
!CY
#
!ZY
#

!NY
#
S<>b<12>wY
PAPSR_TypeA

<01>*<2A>!ISRY
#	!_reserved0Y
#S<>bf
wY
PIPSR_Type<12>

<01>*<2A>!ISRY
#	!_reserved0Y
#!GEY
#!_reserved1Y
#!TY
#
!ITY
#!QY
#
!VY
#
!CY
#
!ZY
#

!NY
#
S<>b<12>
wY
PxPSR_Typel
<01>*<2A>!nPRIVY
#
!SPSELY
#
!FPCAY
#
!_reserved0Y
#S<>b<12>wY
PCONTROL_Type<12>
<01>*<2A><08><03>L
ISER#<03>Y

RESERVED0$# <03>L
ICER@#<23>
<03>Y

RSERVED1V#<23>
<03>L
ISPRr#<23><03>Y

RESERVED2<12>#<23><03>L
ICPR<12>#<23><03>Y

RESERVED3<12>#<23><03>L
IABR<12>#<23><03>Y

7RESERVED4<12>#<23><03>R
<01>
IP#<23><03>Y

<01>RESERVED5 #<23>STIRL#<23>tY
t:
PNVIC_Type

<01>*<2A><0B>
CPUID<12>#ICSRL#VTORL#AIRCRL#SCRL#CCRL#<03>	R
SHP<12>#SHCSRL#$CFSRL#(HFSRL#,DFSRL#0MMFARL#4BFARL#8AFSRL#<<03>
<12>

PFR!#@DFR<12>#HADR<12>#L<03>
<12>
MMFRK#P<03>
<12>
ISAR`#`<03>Y

RESERVED0u#tCPACRL#<23>
Y
t<12>PSCB_Typej
<01>*<2A><03>Y

RESERVED0<12>#ICTR<12>#ACTLRL#PSCnSCB_Type<12>
<01>*<2A>CTRLL#LOADL#VALL#CALIB<12>#PSysTick_Type	
<01>S<>u8Ru16ou32LtI
*<2A><10> <03>
<
PORTz#<03>
Y

<01>RESERVED0<12>#<23>
TERL#<23><03>
Y

RESERVED1<12>#<23>TPRL#<23><03>
Y

RESERVED2<12>#<23>TCRL#<23><03>Y

RESERVED3#<23>IWRL#<23>IRR<12>#<23>IMCRL#<23><03>Y

*RESERVED4M#<23>LARL#<23>LSR<12>#<23><03>Y

RESERVED5<12>#<23>PID4<12>#<23>PID5<12>#<23>PID6<12>#<23>PID7<12>#<23>PID0<12>#<23>PID1<12>#<23>PID2<12>#<23>PID3<12>#<23>CID0<12>#<23>CID1<12>#<23>CID2<12>#<23>CID3<12>#<23>tSPITM_Typeu
<01>*<2A>\CTRLL#CYCCNTL#CPICNTL#EXCCNTL#SLEEPCNTL#LSUCNTL#FOLDCNTL#PCSR<12>#COMP0L# MASK0L#$FUNCTION0L#(<03>Y

RESERVED0<12>#,COMP1L#0MASK1L#4FUNCTION1L#8<03>Y

RESERVED16	#<COMP2L#@MASK2L#DFUNCTION2L#H<03>Y

RESERVED2}	#LCOMP3L#PMASK3L#TFUNCTION3L#XPDWT_TypeQ
<01>*<2A><17>SSPSRL#CSPSRL#<03>Y


RESERVED0<12>	#ACPRL#<03>Y

6RESERVED1
#SPPRL#<23>
<03>Y

<01>
RESERVED2F
#<23>
FFSR<12>#<23>FFCRL#<23>FSCR<12>#<23><03>Y

<01>RESERVED3<12>
#<23>TRIGGER<12>#<23>FIFO0<12>#<23>ITATBCTR2<12>#<23><03>Y

RESERVED4<12>
#<23>ITATBCTR0<12>#<23>FIFO1<12>#<23>ITCTRLL#<23><03>Y

&RESERVED5%#<23>CLAIMSETL#<23>CLAIMCLRL#<23><03>Y

RESERVED7d#<23>DEVID<12>#<23>DEVTYPE<12>#<23>PTPI_Type<12>	
<01>*<2A>,TYPE<12>#CTRLL#RNRL#RBARL#RASRL#RBAR_A1L#RASR_A1L#RBAR_A2L#RASR_A2L# RBAR_A3L#$RASR_A3L#(PMPU_Type<12>
<01>*<2A><03>Y

RESERVED0`#FPCCRL#FPCARL#FPDSCRL#MVFR0<12>#MVFR1<12>#PFPU_Type\
<01>	*<2A>DHCSRL#DCRSRL#DCRDRL#DEMCRL#PCoreDebug_Type<12>
<01>	t
qITM_RxBuffer 


<<3C>
<01>NVIC_SetPriorityGrouping$Y
PriorityGroup\reg_valueY
\PriorityGroupTmpY
;<3B>
<01>NVIC_GetPriorityGroupingY
a__resultY

<<3C>
<01>NVIC_EnableIRQ$<10>IRQn<<3C>
<01>NVIC_DisableIRQ$<10>IRQn;<3B>
<01>NVIC_GetPendingIRQY
$<10>IRQna__resultY

<<3C>
<01>NVIC_SetPendingIRQ$<10>IRQn<<3C>
<01>NVIC_ClearPendingIRQ$<10>IRQn;<3B>
<01>NVIC_GetActiveY
$<10>IRQna__resultY

<<3C>
<01>NVIC_SetPriority$<10>IRQn$Y
priority;<3B>
<01>NVIC_GetPriorityY
$<10>IRQna__resultY

;<3B>
<01>NVIC_EncodePriorityY
$Y
PriorityGroup$Y
PreemptPriority$Y
SubPrioritya__resultY

\PriorityGroupTmpY
\PreemptPriorityBitsY
\SubPriorityBitsY
<<3C>!
<01>NVIC_DecodePriority$Y
Priority$Y
PriorityGroup$<12>pPreemptPriority$<12>pSubPriority\PriorityGroupTmpY
\PreemptPriorityBitsY
\SubPriorityBitsY
"Y
<<3C>!
<01>NVIC_SystemReset;<3B>"
<01>
SysTick_ConfigY
$Y
ticksa__resultY

;<3B>"
<01>
ITM_SendCharY
$Y
cha__resultY

;<3B>"
<01>
ITM_ReceiveChar
a__result

\ch
;<3B>#
<01>
ITM_CheckChar
a__result

<00>&
ITM_RxBuffer
*+,-

(__SYSTEM_STM32F4XX_H <2






..\USER\system_stm32f4xx.h


<01>
..\USER\system_stm32f4xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USERqSystemCoreClockY


"<00><00>SystemCoreClock
/01

6__STM32F4xx_H 
{HSE_VALUE ((uint32_t)8000000)
<01>
HSE_STARTUP_TIMEOUT ((uint16_t)0x05000)
<01>
HSI_VALUE ((uint32_t)16000000)
<01>
__STM32F4XX_STDPERIPH_VERSION_MAIN (0x01)
<01>
__STM32F4XX_STDPERIPH_VERSION_SUB1 (0x04)
<01>
__STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00)
<01>
__STM32F4XX_STDPERIPH_VERSION_RC (0x00)
<01>
__STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24) |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16) |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8) |(__STM32F4XX_STDPERIPH_VERSION_RC))
<01>
__CM4_REV 0x0001
<01>
__MPU_PRESENT 1
<01>
__NVIC_PRIO_BITS 4
<01>
__Vendor_SysTickConfig 0
<01>
__FPU_PRESENT 1<03><03><03>
<01>IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
<01>FLASH_BASE ((uint32_t)0x08000000)
<01>CCMDATARAM_BASE ((uint32_t)0x10000000)
<01>SRAM1_BASE ((uint32_t)0x20000000)
<01>SRAM2_BASE ((uint32_t)0x2001C000)
<01>SRAM3_BASE ((uint32_t)0x20020000)
<01>PERIPH_BASE ((uint32_t)0x40000000)
<01>BKPSRAM_BASE ((uint32_t)0x40024000)
<01>FSMC_R_BASE ((uint32_t)0xA0000000)
<01>CCMDATARAM_BB_BASE ((uint32_t)0x12000000)
<01>SRAM1_BB_BASE ((uint32_t)0x22000000)
<01>SRAM2_BB_BASE ((uint32_t)0x2201C000)
<01>SRAM3_BB_BASE ((uint32_t)0x22400000)
<01>PERIPH_BB_BASE ((uint32_t)0x42000000)
<01>BKPSRAM_BB_BASE ((uint32_t)0x42024000)
<01>SRAM_BASE SRAM1_BASE
<01>SRAM_BB_BASE SRAM1_BB_BASE
<01>APB1PERIPH_BASE PERIPH_BASE
<01>APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
<01>AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
<01>AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)
<01>TIM2_BASE (APB1PERIPH_BASE + 0x0000)
<01>TIM3_BASE (APB1PERIPH_BASE + 0x0400)
<01>TIM4_BASE (APB1PERIPH_BASE + 0x0800)
<01>TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
<01>TIM6_BASE (APB1PERIPH_BASE + 0x1000)
<01>TIM7_BASE (APB1PERIPH_BASE + 0x1400)
<01>TIM12_BASE (APB1PERIPH_BASE + 0x1800)
<01>TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
<01>TIM14_BASE (APB1PERIPH_BASE + 0x2000)
<01>RTC_BASE (APB1PERIPH_BASE + 0x2800)
<01>WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
<01>IWDG_BASE (APB1PERIPH_BASE + 0x3000)
<01>I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)
<01>SPI2_BASE (APB1PERIPH_BASE + 0x3800)
<01>SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
<01>I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)
<01>USART2_BASE (APB1PERIPH_BASE + 0x4400)
<01>USART3_BASE (APB1PERIPH_BASE + 0x4800)
<01>UART4_BASE (APB1PERIPH_BASE + 0x4C00)
<01>UART5_BASE (APB1PERIPH_BASE + 0x5000)
<01>I2C1_BASE (APB1PERIPH_BASE + 0x5400)
<01>I2C2_BASE (APB1PERIPH_BASE + 0x5800)
<01>I2C3_BASE (APB1PERIPH_BASE + 0x5C00)
<01>CAN1_BASE (APB1PERIPH_BASE + 0x6400)
<01>CAN2_BASE (APB1PERIPH_BASE + 0x6800)
<01>PWR_BASE (APB1PERIPH_BASE + 0x7000)
<01>DAC_BASE (APB1PERIPH_BASE + 0x7400)
<01>UART7_BASE (APB1PERIPH_BASE + 0x7800)
<01>UART8_BASE (APB1PERIPH_BASE + 0x7C00)
<01>TIM1_BASE (APB2PERIPH_BASE + 0x0000)
<01>TIM8_BASE (APB2PERIPH_BASE + 0x0400)
<01>USART1_BASE (APB2PERIPH_BASE + 0x1000)
<01>USART6_BASE (APB2PERIPH_BASE + 0x1400)
<01>ADC1_BASE (APB2PERIPH_BASE + 0x2000)
<01>ADC2_BASE (APB2PERIPH_BASE + 0x2100)
<01>ADC3_BASE (APB2PERIPH_BASE + 0x2200)
<01>ADC_BASE (APB2PERIPH_BASE + 0x2300)
<01>SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
<01>SPI1_BASE (APB2PERIPH_BASE + 0x3000)
<01>SPI4_BASE (APB2PERIPH_BASE + 0x3400)
<01>SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)
<01>EXTI_BASE (APB2PERIPH_BASE + 0x3C00)
<01>TIM9_BASE (APB2PERIPH_BASE + 0x4000)
<01>TIM10_BASE (APB2PERIPH_BASE + 0x4400)
<01>TIM11_BASE (APB2PERIPH_BASE + 0x4800)
<01>SPI5_BASE (APB2PERIPH_BASE + 0x5000)
<01>SPI6_BASE (APB2PERIPH_BASE + 0x5400)
<01>SAI1_BASE (APB2PERIPH_BASE + 0x5800)
<01>SAI1_Block_A_BASE (SAI1_BASE + 0x004)
<01>SAI1_Block_B_BASE (SAI1_BASE + 0x024)
<01>LTDC_BASE (APB2PERIPH_BASE + 0x6800)
<01>LTDC_Layer1_BASE (LTDC_BASE + 0x84)
<01>LTDC_Layer2_BASE (LTDC_BASE + 0x104)
<01>GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)
<01>GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)
<01>GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)
<01>GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)
<01>GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)

..\USER\stm32f4xx.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER<12>
IRQn
NonMaskableInt_IRQnrMemoryManagement_IRQntBusFault_IRQnuUsageFault_IRQnvSVCall_IRQn{DebugMonitor_IRQn|PendSV_IRQn~SysTick_IRQnWWDG_IRQnPVD_IRQn
TAMP_STAMP_IRQnRTC_WKUP_IRQnFLASH_IRQnRCC_IRQnEXTI0_IRQnEXTI1_IRQnEXTI2_IRQnEXTI3_IRQn	EXTI4_IRQn
DMA1_Stream0_IRQnDMA1_Stream1_IRQnDMA1_Stream2_IRQn
DMA1_Stream3_IRQnDMA1_Stream4_IRQnDMA1_Stream5_IRQnDMA1_Stream6_IRQnADC_IRQnCAN1_TX_IRQnCAN1_RX0_IRQnCAN1_RX1_IRQnCAN1_SCE_IRQnEXTI9_5_IRQnTIM1_BRK_TIM9_IRQnTIM1_UP_TIM10_IRQnTIM1_TRG_COM_TIM11_IRQnTIM1_CC_IRQnTIM2_IRQnTIM3_IRQnTIM4_IRQnI2C1_EV_IRQnI2C1_ER_IRQn I2C2_EV_IRQn!I2C2_ER_IRQn"SPI1_IRQn#SPI2_IRQn$USART1_IRQn%USART2_IRQn&USART3_IRQn'EXTI15_10_IRQn(RTC_Alarm_IRQn)OTG_FS_WKUP_IRQn*TIM8_BRK_TIM12_IRQn+TIM8_UP_TIM13_IRQn,TIM8_TRG_COM_TIM14_IRQn-TIM8_CC_IRQn.DMA1_Stream7_IRQn/FSMC_IRQn0SDIO_IRQn1TIM5_IRQn2SPI3_IRQn3UART4_IRQn4UART5_IRQn5TIM6_DAC_IRQn6TIM7_IRQn7DMA2_Stream0_IRQn8DMA2_Stream1_IRQn9DMA2_Stream2_IRQn:DMA2_Stream3_IRQn;DMA2_Stream4_IRQn<ETH_IRQn=ETH_WKUP_IRQn>CAN2_TX_IRQn?CAN2_RX0_IRQn<00>CAN2_RX1_IRQn<00>CAN2_SCE_IRQn<00>OTG_FS_IRQn<00>DMA2_Stream5_IRQn<00>DMA2_Stream6_IRQn<00>DMA2_Stream7_IRQn<00>USART6_IRQn<00>I2C3_EV_IRQn<00>I2C3_ER_IRQn<00>OTG_HS_EP1_OUT_IRQn<00>OTG_HS_EP1_IN_IRQn<00>OTG_HS_WKUP_IRQn<00>OTG_HS_IRQn<00>DCMI_IRQn<00>CRYP_IRQn<00>HASH_RNG_IRQn<00>FPU_IRQn<00>PIRQn_Type<12>
<01>Ps32

<01>Ps16


<01>Ps8<10>
<01>
Psc32<12>
<01>

Psc16<12>
<01><10>Psc8<12>
<01>t
Pvs32<12>
<01>t

Pvs16

<01>t<10>Pvs8 
<01>t<12>Pvsc322
<01>t<12>Pvsc16D
<01>t<12>Pvsc8V
<01>Pu32Y

<01>Pu16I

<01>Pu8:

<01>Y
Puc32<12>
<01>I
Puc16<12>
<01>:
Puc8<12>
<01>tY
Pvu32<12>
<01>tI
Pvu16<12>
<01>t:
Pvu8<12>
<01>t<12>Pvuc32
<01>t<12>Pvuc16
<01>t<12>Pvuc8$
<01><13>
RESETSET
PFlagStatus5
<01>(PITStatus5
<01>4<13>
DISABLEENABLE
PFunctionalStaten
<01>/<13>
ERRORSUCCESS
PErrorStatus<12>
<01>,*<2A>PSR<12>#CR1<12>#CR2<12>#SMPR1<12>#SMPR2<12>#JOFR1<12>#JOFR2<12>#JOFR3<12>#JOFR4<12># HTR<12>#$LTR<12>#(SQR1<12>#,SQR2<12>#0SQR3<12>#4JSQR<12>#8JDR1<12>#<JDR2<12>#@JDR3<12>#DJDR4<12>#HDR<12>#LPADC_TypeDef<12>
<01>*<2A>CSR<12>#CCR<12>#CDR<12>#PADC_Common_TypeDef<12>	
<01>*<2A>TIR<12>#TDTR<12>#TDLR<12>#TDHR<12>#PCAN_TxMailBox_TypeDef

<01>*<2A>RIR<12>#RDTR<12>#RDLR<12>#RDHR<12>#PCAN_FIFOMailBox_TypeDefg

<01>*<2A>FR1<12>#FR2<12>#PCAN_FilterRegister_TypeDef<12>

<01>*<2A><19>MCR<12>#MSR<12>#TSR<12>#RF0R<12>#RF1R<12>#IER<12>#ESR<12>#BTR<12>#<03>Y

WRESERVED0X# <03>I

sTxMailBoxt#<23><03><12>


sFIFOMailBox<12>#<23><03>Y

RESERVED1<12>#<23>FMR<12>#<23>FM1R<12>#<23>RESERVED2Y
#<23>FS1R<12>#<23>RESERVED3Y
#<23>FFA1R<12>#<23>RESERVED4Y
#<23>FA1R<12>#<23><03>Y

RESERVED5H#<23><03><12>

sFilterRegistere#<23>PCAN_TypeDef<12>

<01>*<2A>DR<12>#IDR<12>#RESERVED0:
#RESERVED1I
#CR<12>#PCRC_TypeDef<12>
<01>*<2A>8CR<12>#SWTRIGR<12>#DHR12R1<12>#DHR12L1<12>#DHR8R1<12>#DHR12R2<12>#DHR12L2<12>#DHR8R2<12>#DHR12RD<12># DHR12LD<12>#$DHR8RD<12>#(DOR1<12>#,DOR2<12>#0SR<12>#4PDAC_TypeDef<12>
<01>*<2A>IDCODE<12>#CR<12>#APB1FZ<12>#APB2FZ<12>#PDBGMCU_TypeDef<12>

<01>*<2A>,CR<12>#SR<12>#RISR<12>#IER<12>#MISR<12>#ICR<12>#ESCR<12>#ESUR<12>#CWSTRTR<12># CWSIZER<12>#$DR<12>#(PDCMI_TypeDef!
<01>*<2A>CR<12>#NDTR<12>#PAR<12>#M0AR<12>#M1AR<12>#FCR<12>#PDMA_Stream_TypeDef<12>
<01>*<2A>LISR<12>#HISR<12>#LIFCR<12>#HIFCR<12>#PDMA_TypeDef!
<01>*<2A>!<21>CR<12>#ISR<12>#IFCR<12>#FGMAR<12>#FGOR<12>#BGMAR<12>#BGOR<12>#FGPFCCR<12>#FGCOLR<12># BGPFCCR<12>#$BGCOLR<12>#(FGCMAR<12>#,BGCMAR<12>#0OPFCCR<12>#4OCOLR<12>#8OMAR<12>#<OOR<12>#@NLR<12>#DLWR<12>#HAMTCR<12>#L<03> Y

<01>
RESERVEDo#P<03>!<12>
<01>
FGCLUT<12>#<23><03>!<12>
<01>
BGCLUT<12>#<23>PDMA2D_TypeDefl
<01>*<2A>*<2A> MACCR<12>#MACFFR<12>#MACHTHR<12>#MACHTLR<12>#MACMIIAR<12>#MACMIIDR<12>#MACFCR<12>#MACVLANTR<12>#<03>"Y


RESERVED0Q# MACRWUFFR<12>#(MACPMTCSR<12>#,<03>#Y


RESERVED1<12>#0MACSR<12>#8MACIMR<12>#<MACA0HR<12>#@MACA0LR<12>#DMACA1HR<12>#HMACA1LR<12>#LMACA2HR<12>#PMACA2LR<12>#TMACA3HR<12>#XMACA3LR<12>#\<03>$Y

'RESERVED2>#`MMCCR<12>#<23>MMCRIR<12>#<23>MMCTIR<12>#<23>MMCRIMR<12>#<23>MMCTIMR<12>#<23><03>%Y


RESERVED3<12>#<23>MMCTGFSCCR<12>#<23>MMCTGFMSCCR<12>#<23><03>%Y

RESERVED4<12>#<23>MMCTGFCR<12>#<23><03>&Y

	RESERVED5#<23>MMCRFCECR<12>#<23>MMCRFAECR<12>#<23><03>&Y

	RESERVED6Y#<23>MMCRGUFCR<12>#<23><03>'Y

<01>RESERVED7<12>#<23>PTPTSCR<12>#<23>PTPSSIR<12>#<23>PTPTSHR<12>#<23>PTPTSLR<12>#<23>PTPTSHUR<12>#<23>PTPTSLUR<12>#<23>PTPTSAR<12>#<23>PTPTTHR<12>#<23>PTPTTLR<12>#<23>RESERVED8<12>#<23>PTPTSSR<12>#<23><03>(Y

<01>RESERVED9Z#<23>DMABMR<12>#<23> DMATPDR<12>#<23> DMARPDR<12>#<23> DMARDLAR<12>#<23> DMATDLAR<12>#<23> DMASR<12>#<23> DMAOMR<12>#<23> DMAIER<12>#<23> DMAMFBOCR<12>#<23> DMARSWTR<12>#<23> <03>*Y

RESERVED10#<23> DMACHTDR<12>#<23> DMACHRDR<12>#<23> DMACHTBAR<12>#<23> DMACHRBAR<12>#<23> PETH_TypeDef<12>
<01>*<2A>+IMR<12>#EMR<12>#RTSR<12>#FTSR<12>#SWIER<12>#PR<12>#PEXTI_TypeDef<12>
<01>*<2A>,ACR<12>#KEYR<12>#OPTKEYR<12>#SR<12>#CR<12>#OPTCR<12>#OPTCR1<12>#PFLASH_TypeDef<12>
<01>*<2A>, <03>,<12>
BTCRd#PFSMC_Bank1_TypeDef`
<01>*<2A>-<03>-<12>
BWTR<12>#PFSMC_Bank1E_TypeDef<12>
<01>*<2A>.PCR2<12>#SR2<12>#PMEM2<12>#PATT2<12>#RESERVED0Y
#ECCR2<12>#PFSMC_Bank2_TypeDef<12>
<01>*<2A>/PCR3<12>#SR3<12>#PMEM3<12>#PATT3<12>#RESERVED0Y
#ECCR3<12>#PFSMC_Bank3_TypeDef<
<01>*<2A>/PCR4<12>#SR4<12>#PMEM4<12>#PATT4<12>#PIO4<12>#PFSMC_Bank4_TypeDef<12>
<01>*<2A>1(MODER<12>#OTYPER<12>#OSPEEDR<12>#PUPDR<12>#IDR<12>#ODR<12>#BSRRL<12>#BSRRH<12>#LCKR<12>#<03>1<12>

AFR<12># PGPIO_TypeDef

<01>*<2A>2$MEMRMP<12>#PMC<12>#<03>1<12>
EXTICR<12>#<03>1Y


RESERVED<12>#CMPCR<12># PSYSCFG_TypeDef<12>
<01>*<2A>4(CR1<12>#RESERVED0I
#CR2<12>#RESERVED1I
#OAR1<12>#RESERVED2I
#
OAR2<12>#RESERVED3I
#DR<12>#RESERVED4I
#SR1<12>#RESERVED5I
#SR2<12>#RESERVED6I
#CCR<12>#RESERVED7I
#TRISE<12># RESERVED8I
#"FLTR<12>#$RESERVED9I
#&PI2C_TypeDef
<01>*<2A>5KR<12>#PR<12>#RLR<12>#SR<12>#PIWDG_TypeDefh
<01>*<2A>7L<03>5Y


RESERVED0<12>#SSCR<12>#BPCR<12>#AWCR<12>#TWCR<12>#GCR<12>#<03>6Y


RESERVED1#SRCR<12>#$<03>6Y

RESERVED2.#(BCCR<12>#,<03>6Y

RESERVED3V#0IER<12>#4ISR<12>#8ICR<12>#<LIPCR<12>#@CPSR<12>#DCDSR<12>#HPLTDC_TypeDef<12>
<01>*<2A>9DCR<12>#WHPCR<12>#WVPCR<12>#CKCR<12>#PFCR<12>#CACR<12>#DCCR<12>#BFCR<12>#<03>8Y


RESERVED02# CFBAR<12>#(CFBLR<12>#,CFBLNR<12>#0<03>9Y

RESERVED1v#4CLUTWR<12>#@PLTDC_Layer_TypeDef<12>
<01>*<2A>9CR<12>#CSR<12>#PPWR_TypeDef<12>
<01>*<2A>><3E>
CR<12>#PLLCFGR<12>#CFGR<12>#CIR<12>#AHB1RSTR<12>#AHB2RSTR<12>#AHB3RSTR<12>#RESERVED0Y
#APB1RSTR<12># APB2RSTR<12>#$<03>;Y


RESERVED1<12>#(AHB1ENR<12>#0AHB2ENR<12>#4AHB3ENR<12>#8RESERVED2Y
#<APB1ENR<12>#@APB2ENR<12>#D<03><Y


RESERVED3<12>#HAHB1LPENR<12>#PAHB2LPENR<12>#TAHB3LPENR<12>#XRESERVED4Y
#\APB1LPENR<12>#`APB2LPENR<12>#d<03>=Y


RESERVED5<12>#hBDCR<12>#pCSR<12>#t<03>=Y


RESERVED6<12>#xSSCGR<12>#<23>
PLLI2SCFGR<12>#<23>
PLLSAICFGR<12>#<23>
DCKCFGR<12>#<23>
PRCC_TypeDef<12>
<01>*<2A>B<EFBFBD>
TR<12>#DR<12>#CR<12>#ISR<12>#PRER<12>#WUTR<12>#CALIBR<12>#ALRMAR<12>#ALRMBR<12># WPR<12>#$SSR<12>#(SHIFTR<12>#,TSTR<12>#0TSDR<12>#4TSSSR<12>#8CALR<12>#<TAFCR<12>#@ALRMASSR<12>#DALRMBSSR<12>#HRESERVED7Y
#LBKP0R<12>#PBKP1R<12>#TBKP2R<12>#XBKP3R<12>#\BKP4R<12>#`BKP5R<12>#dBKP6R<12>#hBKP7R<12>#lBKP8R<12>#pBKP9R<12>#tBKP10R<12>#xBKP11R<12>#|BKP12R<12>#<23>
BKP13R<12>#<23>
BKP14R<12>#<23>
BKP15R<12>#<23>
BKP16R<12>#<23>
BKP17R<12>#<23>
BKP18R<12>#<23>
BKP19R<12>#<23>
PRTC_TypeDef(
<01>	*<2A>BGCR<12>#PSAI_TypeDefX!
<01>	*<2A>C CR1<12>#CR2<12>#FRCR<12>#SLOTR<12>#IMR<12>#SR<12>#CLRFR<12>#DR<12>#PSAI_Block_TypeDef|!
<01>	*<2A>F<EFBFBD>
POWER<12>#CLKCR<12>#ARG<12>#CMD<12>#RESPCMD#RESP1#RESP2#RESP3#RESP4# DTIMER<12>#$DLEN<12>#(DCTRL<12>#,DCOUNT#0STA#4ICR<12>#8MASK<12>#<<03>EY


RESERVED0<12>"#@FIFOCNT#H<03>EY

RESERVED1<12>"#LFIFO<12>#<23>
PSDIO_TypeDef<12>!
<01>	*<2A>H$CR1<12>#RESERVED0I
#CR2<12>#RESERVED1I
#SR<12>#RESERVED2I
#
DR<12>#RESERVED3I
#CRCPR<12>#RESERVED4I
#RXCRCR<12>#RESERVED5I
#TXCRCR<12>#RESERVED6I
#I2SCFGR<12>#RESERVED7I
#I2SPR<12># RESERVED8I
#"PSPI_TypeDef/#
<01>	*<2A>LTCR1<12>#RESERVED0I
#CR2<12>#RESERVED1I
#SMCR<12>#RESERVED2I
#
DIER<12>#RESERVED3I
#SR<12>#RESERVED4I
#EGR<12>#RESERVED5I
#CCMR1<12>#RESERVED6I
#CCMR2<12>#RESERVED7I
#CCER<12># RESERVED8I
#"CNT<12>#$PSC<12>#(RESERVED9I
#*ARR<12>#,RCR<12>#0RESERVED10I
#2CCR1<12>#4CCR2<12>#8CCR3<12>#<CCR4<12>#@BDTR<12>#DRESERVED11I
#FDCR<12>#HRESERVED12I
#JDMAR<12>#LRESERVED13I
#NOR<12>#PRESERVED14I
#RPTIM_TypeDefb$
<01>
*<2A>NSR<12>#RESERVED0I
#DR<12>#RESERVED1I
#BRR<12>#RESERVED2I
#
CR1<12>#RESERVED3I
#CR2<12>#RESERVED4I
#CR3<12>#RESERVED5I
#GTPR<12>#RESERVED6I
#PUSART_TypeDef<12>&
<01>
*<2A>OCR<12>#CFR<12>#SR<12>#PWWDG_TypeDef{'
<01>
*<2A>S<EFBFBD>
CR<12>#SR<12>#DR<12>#DOUT<12>#DMACR<12>#IMSCR<12>#RISR<12>#MISR<12>#K0LR<12># K0RR<12>#$K1LR<12>#(K1RR<12>#,K2LR<12>#0K2RR<12>#4K3LR<12>#8K3RR<12>#<IV0LR<12>#@IV0RR<12>#DIV1LR<12>#HIV1RR<12>#LCSGCMCCM0R<12>#PCSGCMCCM1R<12>#TCSGCMCCM2R<12>#XCSGCMCCM3R<12>#\CSGCMCCM4R<12>#`CSGCMCCM5R<12>#dCSGCMCCM6R<12>#hCSGCMCCM7R<12>#lCSGCM0R<12>#pCSGCM1R<12>#tCSGCM2R<12>#xCSGCM3R<12>#|CSGCM4R<12>#<23>
CSGCM5R<12>#<23>
CSGCM6R<12>#<23>
CSGCM7R<12>#<23>
PCRYP_TypeDef<12>'
<01>
*<2A>T<EFBFBD>CR<12>#DIN<12>#STR<12>#<03>S<12>
HR<12>)#IMR<12># SR<12>#$<03>TY

3RESERVED*#(<03>T<12>
5CSR3*#<23>
PHASH_TypeDef<12>)
<01>*<2A>T <03>T<12>
HRb*#PHASH_DIGEST_TypeDef^*
<01>*<2A>UCR<12>#SR<12>#DR<12>#PRNG_TypeDef<12>*
<01>
345

__STM32F4xx_ADC_H &
lIS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || ((PERIPH) == ADC2) || ((PERIPH) == ADC3))
sADC_Mode_Independent ((uint32_t)0x00000000)
tADC_DualMode_RegSimult_InjecSimult ((uint32_t)0x00000001)
uADC_DualMode_RegSimult_AlterTrig ((uint32_t)0x00000002)
vADC_DualMode_InjecSimult ((uint32_t)0x00000005)
wADC_DualMode_RegSimult ((uint32_t)0x00000006)
xADC_DualMode_Interl ((uint32_t)0x00000007)
yADC_DualMode_AlterTrig ((uint32_t)0x00000009)
zADC_TripleMode_RegSimult_InjecSimult ((uint32_t)0x00000011)
{ADC_TripleMode_RegSimult_AlterTrig ((uint32_t)0x00000012)
|ADC_TripleMode_InjecSimult ((uint32_t)0x00000015)
}ADC_TripleMode_RegSimult ((uint32_t)0x00000016)
~ADC_TripleMode_Interl ((uint32_t)0x00000017)
ADC_TripleMode_AlterTrig ((uint32_t)0x00000019)
<01>
IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || ((MODE) == ADC_DualMode_InjecSimult) || ((MODE) == ADC_DualMode_RegSimult) || ((MODE) == ADC_DualMode_Interl) || ((MODE) == ADC_DualMode_AlterTrig) || ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || ((MODE) == ADC_TripleMode_InjecSimult) || ((MODE) == ADC_TripleMode_RegSimult) || ((MODE) == ADC_TripleMode_Interl) || ((MODE) == ADC_TripleMode_AlterTrig))
<01>
ADC_Prescaler_Div2 ((uint32_t)0x00000000)
<01>
ADC_Prescaler_Div4 ((uint32_t)0x00010000)
<01>
ADC_Prescaler_Div6 ((uint32_t)0x00020000)
<01>
ADC_Prescaler_Div8 ((uint32_t)0x00030000)
<01>
IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || ((PRESCALER) == ADC_Prescaler_Div4) || ((PRESCALER) == ADC_Prescaler_Div6) || ((PRESCALER) == ADC_Prescaler_Div8))
<01>
ADC_DMAAccessMode_Disabled ((uint32_t)0x00000000)
<01>
ADC_DMAAccessMode_1 ((uint32_t)0x00004000)
<01>
ADC_DMAAccessMode_2 ((uint32_t)0x00008000)
<01>
ADC_DMAAccessMode_3 ((uint32_t)0x0000C000)
<01>
IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || ((MODE) == ADC_DMAAccessMode_1) || ((MODE) == ADC_DMAAccessMode_2) || ((MODE) == ADC_DMAAccessMode_3))
<01>
ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000)
<01>
ADC_TwoSamplingDelay_6Cycles ((uint32_t)0x00000100)
<01>
ADC_TwoSamplingDelay_7Cycles ((uint32_t)0x00000200)
<01>
ADC_TwoSamplingDelay_8Cycles ((uint32_t)0x00000300)
<01>
ADC_TwoSamplingDelay_9Cycles ((uint32_t)0x00000400)
<01>
ADC_TwoSamplingDelay_10Cycles ((uint32_t)0x00000500)
<01>
ADC_TwoSamplingDelay_11Cycles ((uint32_t)0x00000600)
<01>
ADC_TwoSamplingDelay_12Cycles ((uint32_t)0x00000700)
<01>
ADC_TwoSamplingDelay_13Cycles ((uint32_t)0x00000800)
<01>
ADC_TwoSamplingDelay_14Cycles ((uint32_t)0x00000900)
<01>
ADC_TwoSamplingDelay_15Cycles ((uint32_t)0x00000A00)
<01>
ADC_TwoSamplingDelay_16Cycles ((uint32_t)0x00000B00)
<01>
ADC_TwoSamplingDelay_17Cycles ((uint32_t)0x00000C00)
<01>
ADC_TwoSamplingDelay_18Cycles ((uint32_t)0x00000D00)
<01>
ADC_TwoSamplingDelay_19Cycles ((uint32_t)0x00000E00)
<01>
ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00)
<01>
IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
<01>
ADC_Resolution_12b ((uint32_t)0x00000000)
<01>
ADC_Resolution_10b ((u
..\FWLIB\inc\stm32f4xx_adc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>ADC_ResolutionY
#ADC_ScanConvMode<10>#ADC_ContinuousConvMode<10>#ADC_ExternalTrigConvEdgeY
#ADC_ExternalTrigConvY
#ADC_DataAlignY
#ADC_NbrOfConversion:
#PADC_InitTypeDef<12>
O*<2A>ADC_ModeY
#ADC_PrescalerY
#ADC_DMAAccessModeY
#ADC_TwoSamplingDelayY
#PADC_CommonInitTypeDef<12>

d
789

__STM32F4xx_CRC_H &XL






..\FWLIB\inc\..\USER\stm32f4xx_crc.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_crc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
;<=

__STM32F4xx_DBGMCU_H %
5DBGMCU_SLEEP ((uint32_t)0x00000001)
6DBGMCU_STOP ((uint32_t)0x00000002)
7DBGMCU_STANDBY ((uint32_t)0x00000004)
8IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
:DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
;DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
<DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
=DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
>DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
?DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
@DBGMCU_TIM12_STOP ((uint32_t)0x00000040)
ADBGMCU_TIM13_STOP ((uint32_t)0x00000080)
BDBGMCU_TIM14_STOP ((uint32_t)0x00000100)
CDBGMCU_RTC_STOP ((uint32_t)0x00000400)
DDBGMCU_WWDG_STOP ((uint32_t)0x00000800)
EDBGMCU_IWDG_STOP ((uint32_t)0x00001000)
FDBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
GDBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
HDBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
IDBGMCU_CAN1_STOP ((uint32_t)0x02000000)
JDBGMCU_CAN2_STOP ((uint32_t)0x04000000)
KIS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
MDBGMCU_TIM1_STOP ((uint32_t)0x00000001)
NDBGMCU_TIM8_STOP ((uint32_t)0x00000002)
ODBGMCU_TIM9_STOP ((uint32_t)0x00010000)
PDBGMCU_TIM10_STOP ((uint32_t)0x00020000)
QDBGMCU_TIM11_STOP ((uint32_t)0x00040000)
RIS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))XO






..\FWLIB\inc\..\USER\stm32f4xx_dbgmcu.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_dbgmcu.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
?@A

__STM32F4xx_DMA_H &
vIS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || ((PERIPH) == DMA1_Stream1) || ((PERIPH) == DMA1_Stream2) || ((PERIPH) == DMA1_Stream3) || ((PERIPH) == DMA1_Stream4) || ((PERIPH) == DMA1_Stream5) || ((PERIPH) == DMA1_Stream6) || ((PERIPH) == DMA1_Stream7) || ((PERIPH) == DMA2_Stream0) || ((PERIPH) == DMA2_Stream1) || ((PERIPH) == DMA2_Stream2) || ((PERIPH) == DMA2_Stream3) || ((PERIPH) == DMA2_Stream4) || ((PERIPH) == DMA2_Stream5) || ((PERIPH) == DMA2_Stream6) || ((PERIPH) == DMA2_Stream7))
<01>
IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || ((CONTROLLER) == DMA2))
<01>
DMA_Channel_0 ((uint32_t)0x00000000)
<01>
DMA_Channel_1 ((uint32_t)0x02000000)
<01>
DMA_Channel_2 ((uint32_t)0x04000000)
<01>
DMA_Channel_3 ((uint32_t)0x06000000)
<01>
DMA_Channel_4 ((uint32_t)0x08000000)
<01>
DMA_Channel_5 ((uint32_t)0x0A000000)
<01>
DMA_Channel_6 ((uint32_t)0x0C000000)
<01>
DMA_Channel_7 ((uint32_t)0x0E000000)
<01>
IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || ((CHANNEL) == DMA_Channel_1) || ((CHANNEL) == DMA_Channel_2) || ((CHANNEL) == DMA_Channel_3) || ((CHANNEL) == DMA_Channel_4) || ((CHANNEL) == DMA_Channel_5) || ((CHANNEL) == DMA_Channel_6) || ((CHANNEL) == DMA_Channel_7))
<01>
DMA_DIR_PeripheralToMemory ((uint32_t)0x00000000)
<01>
DMA_DIR_MemoryToPeripheral ((uint32_t)0x00000040)
<01>
DMA_DIR_MemoryToMemory ((uint32_t)0x00000080)
<01>
IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || ((DIRECTION) == DMA_DIR_MemoryToPeripheral) || ((DIRECTION) == DMA_DIR_MemoryToMemory))
<01>
IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
<01>
DMA_PeripheralInc_Enable ((uint32_t)0x00000200)
<01>
DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
<01>
IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || ((STATE) == DMA_PeripheralInc_Disable))
<01>
DMA_MemoryInc_Enable ((uint32_t)0x00000400)
<01>
DMA_MemoryInc_Disable ((uint32_t)0x00000000)
<01>
IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || ((STATE) == DMA_MemoryInc_Disable))
<01>
DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
<01>
DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000800)
<01>
DMA_PeripheralDataSize_Word ((uint32_t)0x00001000)
<01>
IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || ((SIZE) == DMA_PeripheralDataSize_HalfWord) || ((SIZE) == DMA_PeripheralDataSize_Word))
<01>
DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
<01>
DMA_MemoryDataSize_HalfWord ((uint32_t)0x00002000)
<01>
DMA_MemoryDataSize_Word ((uint32_t)0x00004000)
<01>
IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || ((SIZE) == DMA_MemoryDataSize_HalfWord) || ((SIZE) == DMA_MemoryDataSize_Word ))
<01>
DMA_Mode_Normal ((uint32_t)0x00000000)
<01>
DMA_Mode_Circular ((uint32_t)0x00000100)
<01>
IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || ((MODE) == DMA_Mode_Circular))
<01>DMA_Priority_Low ((uint32_t)0x00000000)
<01>DMA_Priority_Medium ((uint32_t)0x00010000)
<01>DMA_Priority_High ((uint32_t)0x00020000)
<01>DMA_Priority_VeryHigh ((uint32_t)0x00030000)
<01>IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low ) || ((PRIORITY) == DMA_Priority_Medium) || ((PRIORITY) == DMA_Priority_High) || ((PRIORITY) == DMA_Priority_VeryHigh))
<01>DMA_FIFOMode_Disable ((uint32_t)0x00000000)
<01>DMA_FIFOMode_Enable ((uint32_t)0x00000004)
<01>IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || ((STATE) == DMA_FIFOMode_Enable))
<01>DMA_FIFOThreshold_1QuarterFull ((uint32_t)0x00000000)
<01>DMA_FIFOThreshold_HalfFull ((uint32_t)0x00000001)
<01>DMA_FIFOThreshold_3QuartersFull ((uint32_t)0x00000002)
<01>DMA_FIFOThreshold_Full ((uint32_t)0x00000003)
<01>IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || ((THRESHOLD) == DMA_FIFOThreshold_HalfFull) || ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || ((THRESHOLD) == DMA_FIFOThreshold_Full))
<01>DMA_MemoryBurst_Single (
..\FWLIB\inc\stm32f4xx_dma.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A><DMA_ChannelY
#DMA_PeripheralBaseAddrY
#DMA_Memory0BaseAddrY
#DMA_DIRY
#DMA_BufferSizeY
#DMA_PeripheralIncY
#DMA_MemoryIncY
#DMA_PeripheralDataSizeY
#DMA_MemoryDataSizeY
# DMA_ModeY
#$DMA_PriorityY
#(DMA_FIFOModeY
#,DMA_FIFOThresholdY
#0DMA_MemoryBurstY
#4DMA_PeripheralBurstY
#8PDMA_InitTypeDef<12>
n
CDE

__STM32F4xx_EXTI_H &
<IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
IIS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || ((TRIGGER) == EXTI_Trigger_Falling) || ((TRIGGER) == EXTI_Trigger_Rising_Falling))
iEXTI_Line0 ((uint32_t)0x00001)
jEXTI_Line1 ((uint32_t)0x00002)
kEXTI_Line2 ((uint32_t)0x00004)
lEXTI_Line3 ((uint32_t)0x00008)
mEXTI_Line4 ((uint32_t)0x00010)
nEXTI_Line5 ((uint32_t)0x00020)
oEXTI_Line6 ((uint32_t)0x00040)
pEXTI_Line7 ((uint32_t)0x00080)
qEXTI_Line8 ((uint32_t)0x00100)
rEXTI_Line9 ((uint32_t)0x00200)
sEXTI_Line10 ((uint32_t)0x00400)
tEXTI_Line11 ((uint32_t)0x00800)
uEXTI_Line12 ((uint32_t)0x01000)
vEXTI_Line13 ((uint32_t)0x02000)
wEXTI_Line14 ((uint32_t)0x04000)
xEXTI_Line15 ((uint32_t)0x08000)
yEXTI_Line16 ((uint32_t)0x10000)
zEXTI_Line17 ((uint32_t)0x20000)
{EXTI_Line18 ((uint32_t)0x40000)
|EXTI_Line19 ((uint32_t)0x80000)
}EXTI_Line20 ((uint32_t)0x00100000)
~EXTI_Line21 ((uint32_t)0x00200000)
EXTI_Line22 ((uint32_t)0x00400000)
<01>
IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
<01>
IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || ((LINE) == EXTI_Line22))XM






..\FWLIB\inc\..\USER\stm32f4xx_exti.h
stm32f4xx.h

<01>

..\FWLIB\inc\stm32f4xx_exti.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER<13>

EXTI_Mode_InterruptEXTI_Mode_EventPEXTIMode_TypeDef<12>
:<13>
EXTI_Trigger_RisingEXTI_Trigger_FallingEXTI_Trigger_Rising_FallingPEXTITrigger_TypeDef

G*<2A>EXTI_LineY
#EXTI_Mode<12>#EXTI_Trigger^
#EXTI_LineCmd<10>#PEXTI_InitTypeDefy

]
GHI

__STM32F4xx_FLASH_H &
JFLASH_Latency_0 ((uint8_t)0x0000)
KFLASH_Latency_1 ((uint8_t)0x0001)
LFLASH_Latency_2 ((uint8_t)0x0002)
MFLASH_Latency_3 ((uint8_t)0x0003)
NFLASH_Latency_4 ((uint8_t)0x0004)
OFLASH_Latency_5 ((uint8_t)0x0005)
PFLASH_Latency_6 ((uint8_t)0x0006)
QFLASH_Latency_7 ((uint8_t)0x0007)
RFLASH_Latency_8 ((uint8_t)0x0008)
SFLASH_Latency_9 ((uint8_t)0x0009)
TFLASH_Latency_10 ((uint8_t)0x000A)
UFLASH_Latency_11 ((uint8_t)0x000B)
VFLASH_Latency_12 ((uint8_t)0x000C)
WFLASH_Latency_13 ((uint8_t)0x000D)
XFLASH_Latency_14 ((uint8_t)0x000E)
YFLASH_Latency_15 ((uint8_t)0x000F)
\IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || ((LATENCY) == FLASH_Latency_1) || ((LATENCY) == FLASH_Latency_2) || ((LATENCY) == FLASH_Latency_3) || ((LATENCY) == FLASH_Latency_4) || ((LATENCY) == FLASH_Latency_5) || ((LATENCY) == FLASH_Latency_6) || ((LATENCY) == FLASH_Latency_7) || ((LATENCY) == FLASH_Latency_8) || ((LATENCY) == FLASH_Latency_9) || ((LATENCY) == FLASH_Latency_10) || ((LATENCY) == FLASH_Latency_11) || ((LATENCY) == FLASH_Latency_12) || ((LATENCY) == FLASH_Latency_13) || ((LATENCY) == FLASH_Latency_14) || ((LATENCY) == FLASH_Latency_15))
sVoltageRange_1 ((uint8_t)0x00)
tVoltageRange_2 ((uint8_t)0x01)
uVoltageRange_3 ((uint8_t)0x02)
vVoltageRange_4 ((uint8_t)0x03)
xIS_VOLTAGERANGE(RANGE) (((RANGE) == VoltageRange_1) || ((RANGE) == VoltageRange_2) || ((RANGE) == VoltageRange_3) || ((RANGE) == VoltageRange_4))
<01>
FLASH_Sector_0 ((uint16_t)0x0000)
<01>
FLASH_Sector_1 ((uint16_t)0x0008)
<01>
FLASH_Sector_2 ((uint16_t)0x0010)
<01>
FLASH_Sector_3 ((uint16_t)0x0018)
<01>
FLASH_Sector_4 ((uint16_t)0x0020)
<01>
FLASH_Sector_5 ((uint16_t)0x0028)
<01>
FLASH_Sector_6 ((uint16_t)0x0030)
<01>
FLASH_Sector_7 ((uint16_t)0x0038)
<01>
FLASH_Sector_8 ((uint16_t)0x0040)
<01>
FLASH_Sector_9 ((uint16_t)0x0048)
<01>
FLASH_Sector_10 ((uint16_t)0x0050)
<01>
FLASH_Sector_11 ((uint16_t)0x0058)
<01>
FLASH_Sector_12 ((uint16_t)0x0080)
<01>
FLASH_Sector_13 ((uint16_t)0x0088)
<01>
FLASH_Sector_14 ((uint16_t)0x0090)
<01>
FLASH_Sector_15 ((uint16_t)0x0098)
<01>
FLASH_Sector_16 ((uint16_t)0x00A0)
<01>
FLASH_Sector_17 ((uint16_t)0x00A8)
<01>
FLASH_Sector_18 ((uint16_t)0x00B0)
<01>
FLASH_Sector_19 ((uint16_t)0x00B8)
<01>
FLASH_Sector_20 ((uint16_t)0x00C0)
<01>
FLASH_Sector_21 ((uint16_t)0x00C8)
<01>
FLASH_Sector_22 ((uint16_t)0x00D0)
<01>
FLASH_Sector_23 ((uint16_t)0x00D8)
<01>
IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_Sector_0) || ((SECTOR) == FLASH_Sector_1) || ((SECTOR) == FLASH_Sector_2) || ((SECTOR) == FLASH_Sector_3) || ((SECTOR) == FLASH_Sector_4) || ((SECTOR) == FLASH_Sector_5) || ((SECTOR) == FLASH_Sector_6) || ((SECTOR) == FLASH_Sector_7) || ((SECTOR) == FLASH_Sector_8) || ((SECTOR) == FLASH_Sector_9) || ((SECTOR) == FLASH_Sector_10) || ((SECTOR) == FLASH_Sector_11) || ((SECTOR) == FLASH_Sector_12) || ((SECTOR) == FLASH_Sector_13) || ((SECTOR) == FLASH_Sector_14) || ((SECTOR) == FLASH_Sector_15) || ((SECTOR) == FLASH_Sector_16) || ((SECTOR) == FLASH_Sector_17) || ((SECTOR) == FLASH_Sector_18) || ((SECTOR) == FLASH_Sector_19) || ((SECTOR) == FLASH_Sector_20) || ((SECTOR) == FLASH_Sector_21) || ((SECTOR) == FLASH_Sector_22) || ((SECTOR) == FLASH_Sector_23))
<01>
IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) || (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) <= 0x1FFF7A0F)))
<01>
OB_WRP_Sector_0 ((uint32_t)0x00000001)
<01>
OB_WRP_Sector_1 ((uint32_t)0x00000002)
<01>
OB_WRP_Sector_2 ((uint32_t)0x00000004)
<01>
OB_WRP_Sector_3 ((uint32_t)0x00000008)
<01>
OB_WRP_Sector_4 ((uint32_t)0x00000010)
<01>
OB_WRP_Sector_5 ((uint32_t)0x00000020)
<01>
OB_WRP_Sector_6 ((uin
..\FWLIB\inc\stm32f4xx_flash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER<13>
FLASH_BUSY
FLASH_ERROR_RDFLASH_ERROR_PGSFLASH_ERROR_PGPFLASH_ERROR_PGAFLASH_ERROR_WRPFLASH_ERROR_PROGRAMFLASH_ERROR_OPERATIONFLASH_COMPLETE	PFLASH_Status<12>
?
KLM

__STM32F4xx_GPIO_H &
2IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || ((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) || ((PERIPH) == GPIOE) || ((PERIPH) == GPIOF) || ((PERIPH) == GPIOG) || ((PERIPH) == GPIOH) || ((PERIPH) == GPIOI) || ((PERIPH) == GPIOJ) || ((PERIPH) == GPIOK))
HIS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
SIS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
bGPIO_Speed_2MHz GPIO_Low_Speed
cGPIO_Speed_25MHz GPIO_Medium_Speed
dGPIO_Speed_50MHz GPIO_Fast_Speed
eGPIO_Speed_100MHz GPIO_High_Speed
gIS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Low_Speed) || ((SPEED) == GPIO_Medium_Speed) || ((SPEED) == GPIO_Fast_Speed)|| ((SPEED) == GPIO_High_Speed))
sIS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || ((PUPD) == GPIO_PuPd_DOWN))
~IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
<01>
GPIO_Pin_0 ((uint16_t)0x0001)
<01>
GPIO_Pin_1 ((uint16_t)0x0002)
<01>
GPIO_Pin_2 ((uint16_t)0x0004)
<01>
GPIO_Pin_3 ((uint16_t)0x0008)
<01>
GPIO_Pin_4 ((uint16_t)0x0010)
<01>
GPIO_Pin_5 ((uint16_t)0x0020)
<01>
GPIO_Pin_6 ((uint16_t)0x0040)
<01>
GPIO_Pin_7 ((uint16_t)0x0080)
<01>
GPIO_Pin_8 ((uint16_t)0x0100)
<01>
GPIO_Pin_9 ((uint16_t)0x0200)
<01>
GPIO_Pin_10 ((uint16_t)0x0400)
<01>
GPIO_Pin_11 ((uint16_t)0x0800)
<01>
GPIO_Pin_12 ((uint16_t)0x1000)
<01>
GPIO_Pin_13 ((uint16_t)0x2000)
<01>
GPIO_Pin_14 ((uint16_t)0x4000)
<01>
GPIO_Pin_15 ((uint16_t)0x8000)
<01>
GPIO_Pin_All ((uint16_t)0xFFFF)
<01>
GPIO_PIN_MASK ((uint32_t)0x0000FFFF)
<01>
IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
<01>
IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || ((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || ((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || ((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || ((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || ((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || ((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || ((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15))
<01>
GPIO_PinSource0 ((uint8_t)0x00)
<01>
GPIO_PinSource1 ((uint8_t)0x01)
<01>
GPIO_PinSource2 ((uint8_t)0x02)
<01>
GPIO_PinSource3 ((uint8_t)0x03)
<01>
GPIO_PinSource4 ((uint8_t)0x04)
<01>
GPIO_PinSource5 ((uint8_t)0x05)
<01>
GPIO_PinSource6 ((uint8_t)0x06)
<01>
GPIO_PinSource7 ((uint8_t)0x07)
<01>
GPIO_PinSource8 ((uint8_t)0x08)
<01>
GPIO_PinSource9 ((uint8_t)0x09)
<01>
GPIO_PinSource10 ((uint8_t)0x0A)
<01>
GPIO_PinSource11 ((uint8_t)0x0B)
<01>
GPIO_PinSource12 ((uint8_t)0x0C)
<01>
GPIO_PinSource13 ((uint8_t)0x0D)
<01>
GPIO_PinSource14 ((uint8_t)0x0E)
<01>
GPIO_PinSource15 ((uint8_t)0x0F)
<01>
IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || ((PINSOURCE) == GPIO_PinSource1) || ((PINSOURCE) == GPIO_PinSource2) || ((PINSOURCE) == GPIO_PinSource3) || ((PINSOURCE) == GPIO_PinSource4) || ((PINSOURCE) == GPIO_PinSource5) || ((PINSOURCE) == GPIO_PinSource6) || ((PINSOURCE) == GPIO_PinSource7) || ((PINSOURCE) == GPIO_PinSource8) || ((PINSOURCE) == GPIO_PinSource9) || ((PINSOURCE) == GPIO_PinSource10) || ((PINSOURCE) == GPIO_PinSource11) || ((PINSOURCE) == GPIO_PinSource12) || ((PINSOURCE) == GPIO_PinSource13) || ((PINSOURCE) == GPIO_PinSource14) || ((PINSOURCE) == GPIO_PinSource15))
<01>
GPIO_AF_RTC_50Hz ((uint8_t)0x00)
<01>
GPIO_AF_MCO ((uint8_t)0x00)
<01>
GPIO_AF_TAMPER ((uint8_t)0x00)
<01>
GPIO_AF_SWJ ((uint8_t)0x00)
<01>
GPIO_AF_TRACE ((uint8_t)0x00)
<01>
GPIO_AF_TIM1 ((uint8_t)0x01)
<01>GPIO_AF_TIM2 ((uint8_t)0x01)
<01>GPIO_AF_TIM3 ((uint8_t)0x02)
<01>GPIO_AF_TIM4 ((uint8_t)0x02)
<01>GPIO_AF_TIM5 ((uint8_t)0x02)
<01>GPIO_AF_TIM8 ((uint8_t)0x03)
<01>GPIO_AF_TIM9 ((uint8_t)0x03)
<01>GPIO_AF_TIM
..\FWLIB\inc\stm32f4xx_gpio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER<13>
GPIO_Mode_INGPIO_Mode_OUT
GPIO_Mode_AFGPIO_Mode_ANPGPIOMode_TypeDef<12>
G<13>
GPIO_OType_PPGPIO_OType_OD
PGPIOOType_TypeDef"

R<13>
GPIO_Low_SpeedGPIO_Medium_Speed
GPIO_Fast_SpeedGPIO_High_SpeedPGPIOSpeed_TypeDefb

_<13>
GPIO_PuPd_NOPULLGPIO_PuPd_UP
GPIO_PuPd_DOWNPGPIOPuPd_TypeDef<12>

r<13>
Bit_RESETBit_SET
PBitAction 
}*<2A>GPIO_PinY
#GPIO_Mode

#GPIO_Speed<12>
#GPIO_OTypeI
#GPIO_PuPd#PGPIO_InitTypeDefN
<01>

OPQ

__STM32F4xx_I2C_H &
RIS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || ((PERIPH) == I2C2) || ((PERIPH) == I2C3))
ZIS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
dI2C_Mode_I2C ((uint16_t)0x0000)
eI2C_Mode_SMBusDevice ((uint16_t)0x0002)
fI2C_Mode_SMBusHost ((uint16_t)0x000A)
gIS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || ((MODE) == I2C_Mode_SMBusDevice) || ((MODE) == I2C_Mode_SMBusHost))
rI2C_DutyCycle_16_9 ((uint16_t)0x4000)
sI2C_DutyCycle_2 ((uint16_t)0xBFFF)
tIS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || ((CYCLE) == I2C_DutyCycle_2))
~I2C_Ack_Enable ((uint16_t)0x0400)
I2C_Ack_Disable ((uint16_t)0x0000)
<01>
IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || ((STATE) == I2C_Ack_Disable))
<01>
I2C_Direction_Transmitter ((uint8_t)0x00)
<01>
I2C_Direction_Receiver ((uint8_t)0x01)
<01>
IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || ((DIRECTION) == I2C_Direction_Receiver))
<01>
I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
<01>
I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
<01>
IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
<01>
I2C_Register_CR1 ((uint8_t)0x00)
<01>
I2C_Register_CR2 ((uint8_t)0x04)
<01>
I2C_Register_OAR1 ((uint8_t)0x08)
<01>
I2C_Register_OAR2 ((uint8_t)0x0C)
<01>
I2C_Register_DR ((uint8_t)0x10)
<01>
I2C_Register_SR1 ((uint8_t)0x14)
<01>
I2C_Register_SR2 ((uint8_t)0x18)
<01>
I2C_Register_CCR ((uint8_t)0x1C)
<01>
I2C_Register_TRISE ((uint8_t)0x20)
<01>
IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || ((REGISTER) == I2C_Register_CR2) || ((REGISTER) == I2C_Register_OAR1) || ((REGISTER) == I2C_Register_OAR2) || ((REGISTER) == I2C_Register_DR) || ((REGISTER) == I2C_Register_SR1) || ((REGISTER) == I2C_Register_SR2) || ((REGISTER) == I2C_Register_CCR) || ((REGISTER) == I2C_Register_TRISE))
<01>
I2C_NACKPosition_Next ((uint16_t)0x0800)
<01>
I2C_NACKPosition_Current ((uint16_t)0xF7FF)
<01>
IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || ((POSITION) == I2C_NACKPosition_Current))
<01>
I2C_SMBusAlert_Low ((uint16_t)0x2000)
<01>
I2C_SMBusAlert_High ((uint16_t)0xDFFF)
<01>
IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || ((ALERT) == I2C_SMBusAlert_High))
<01>
I2C_PECPosition_Next ((uint16_t)0x0800)
<01>
I2C_PECPosition_Current ((uint16_t)0xF7FF)
<01>
IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || ((POSITION) == I2C_PECPosition_Current))
<01>
I2C_IT_BUF ((uint16_t)0x0400)
<01>
I2C_IT_EVT ((uint16_t)0x0200)
<01>
I2C_IT_ERR ((uint16_t)0x0100)
<01>
IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
<01>
I2C_IT_SMBALERT ((uint32_t)0x01008000)
<01>
I2C_IT_TIMEOUT ((uint32_t)0x01004000)
<01>
I2C_IT_PECERR ((uint32_t)0x01001000)
<01>
I2C_IT_OVR ((uint32_t)0x01000800)
<01>
I2C_IT_AF ((uint32_t)0x01000400)
<01>
I2C_IT_ARLO ((uint32_t)0x01000200)
<01>
I2C_IT_BERR ((uint32_t)0x01000100)
<01>
I2C_IT_TXE ((uint32_t)0x06000080)
<01>
I2C_IT_RXNE ((uint32_t)0x06000040)
<01>
I2C_IT_STOPF ((uint32_t)0x02000010)
<01>
I2C_IT_ADD10 ((uint32_t)0x02000008)
<01>
I2C_IT_BTF ((uint32_t)0x02000004)
<01>
I2C_IT_ADDR ((uint32_t)0x02000002)
<01>
I2C_IT_SB ((uint32_t)0x02000001)
<01>
IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
<01>
IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
<01>I2C_FLAG_DUALF ((uint32_t)0x00800000)
<01>I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
<01>I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
<01>I2C_FLAG_GENCALL ((uint32_t)0x00100000)
<01>I2C_FLAG_TRA ((uint32_t)0x00040000)
<01>I2C_FLAG_BUSY ((uint32_t)0x00020000)
<01>I2C_FLAG_MSL ((uint32_t)0x00010000)
<01>I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
<01>I2C_FLAG_TIMEO
..\FWLIB\inc\stm32f4xx_i2c.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>I2C_ClockSpeedY
#I2C_ModeI
#I2C_DutyCycleI
#I2C_OwnAddress1I
#I2C_AckI
#
I2C_AcknowledgedAddressI
#PI2C_InitTypeDef<12>
I
STU

__STM32F4xx_IWDG_H &
:IWDG_WriteAccess_Enable ((uint16_t)0x5555)
;IWDG_WriteAccess_Disable ((uint16_t)0x0000)
<IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || ((ACCESS) == IWDG_WriteAccess_Disable))
EIWDG_Prescaler_4 ((uint8_t)0x00)
FIWDG_Prescaler_8 ((uint8_t)0x01)
GIWDG_Prescaler_16 ((uint8_t)0x02)
HIWDG_Prescaler_32 ((uint8_t)0x03)
IIWDG_Prescaler_64 ((uint8_t)0x04)
JIWDG_Prescaler_128 ((uint8_t)0x05)
KIWDG_Prescaler_256 ((uint8_t)0x06)
LIS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || ((PRESCALER) == IWDG_Prescaler_8) || ((PRESCALER) == IWDG_Prescaler_16) || ((PRESCALER) == IWDG_Prescaler_32) || ((PRESCALER) == IWDG_Prescaler_64) || ((PRESCALER) == IWDG_Prescaler_128)|| ((PRESCALER) == IWDG_Prescaler_256))
ZIWDG_FLAG_PVU ((uint16_t)0x0001)
[IWDG_FLAG_RVU ((uint16_t)0x0002)
\IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
]IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)XM






..\FWLIB\inc\..\USER\stm32f4xx_iwdg.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_iwdg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
WXY

__STM32F4xx_PWR_H &
:PWR_PVDLevel_0 PWR_CR_PLS_LEV0
;PWR_PVDLevel_1 PWR_CR_PLS_LEV1
<PWR_PVDLevel_2 PWR_CR_PLS_LEV2
=PWR_PVDLevel_3 PWR_CR_PLS_LEV3
>PWR_PVDLevel_4 PWR_CR_PLS_LEV4
?PWR_PVDLevel_5 PWR_CR_PLS_LEV5
@PWR_PVDLevel_6 PWR_CR_PLS_LEV6
APWR_PVDLevel_7 PWR_CR_PLS_LEV7
CIS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
OPWR_MainRegulator_ON ((uint32_t)0x00000000)
PPWR_LowPowerRegulator_ON PWR_CR_LPDS
SPWR_Regulator_ON PWR_MainRegulator_ON
TPWR_Regulator_LowPower PWR_LowPowerRegulator_ON
VIS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || ((REGULATOR) == PWR_LowPowerRegulator_ON))
`PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
aPWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
cIS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
mPWR_STOPEntry_WFI ((uint8_t)0x01)
nPWR_STOPEntry_WFE ((uint8_t)0x02)
oIS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
wPWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
xPWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
yPWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
zIS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
<01>
PWR_FLAG_WU PWR_CSR_WUF
<01>
PWR_FLAG_SB PWR_CSR_SBF
<01>
PWR_FLAG_PVDO PWR_CSR_PVDO
<01>
PWR_FLAG_BRR PWR_CSR_BRR
<01>
PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
<01>
PWR_FLAG_ODRDY PWR_CSR_ODRDY
<01>
PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
<01>
PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
<01>
PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
<01>
IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
<01>
IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || ((FLAG) == PWR_FLAG_UDRDY))XL






..\FWLIB\inc\..\USER\stm32f4xx_pwr.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_pwr.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
[\]

__STM32F4xx_RCC_H %
ARCC_HSE_OFF ((uint8_t)0x00)
BRCC_HSE_ON ((uint8_t)0x01)
CRCC_HSE_Bypass ((uint8_t)0x05)
DIS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || ((HSE) == RCC_HSE_Bypass))
MRCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
NRCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
OIS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) || ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
XRCC_PLLSource_HSI ((uint32_t)0x00000000)
YRCC_PLLSource_HSE ((uint32_t)0x00400000)
ZIS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || ((SOURCE) == RCC_PLLSource_HSE))
\IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
]IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
^IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
_IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
aIS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bIS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
cIS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
eIS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
fIS_RCC_PLLSAIN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
gIS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
hIS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
jIS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
kIS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
mRCC_PLLSAIDivR_Div2 ((uint32_t)0x00000000)
nRCC_PLLSAIDivR_Div4 ((uint32_t)0x00010000)
oRCC_PLLSAIDivR_Div8 ((uint32_t)0x00020000)
pRCC_PLLSAIDivR_Div16 ((uint32_t)0x00030000)
qIS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDivR_Div2) || ((VALUE) == RCC_PLLSAIDivR_Div4) || ((VALUE) == RCC_PLLSAIDivR_Div8) || ((VALUE) == RCC_PLLSAIDivR_Div16))
}RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
~RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
<01>
IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || ((SOURCE) == RCC_SYSCLKSource_HSE) || ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
<01>
RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
<01>
RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
<01>
RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
<01>
RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
<01>
RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
<01>
RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
<01>
RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
<01>
RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
<01>
RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
<01>
IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || ((HCLK) == RCC_SYSCLK_Div512))
<01>
RCC_HCLK_Div1 ((uint32_t)0x00000000)
<01>
RCC_HCLK_Div2 ((uint32_t)0x00001000)
<01>
RCC_HCLK_Div4 ((uint32_t)0x00001400)
<01>
RCC_HCLK_Div8 ((uint32_t)0x00001800)
<01>
RCC_HCLK_Div16 ((uint32_t)0x00001C00)
<01>
IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || ((PCLK) == RCC_HCLK_Div16))
<01>
RCC_IT_LSIRDY ((uint8_t)0x01)
<01>
RCC_IT_LSERDY ((uint8_t)0x02)
<01>
RCC_IT_HSIRDY ((uint8_t)0x04)
<01>
RCC_IT_HSERDY ((uint8_t)0x08)
<01>
RCC_IT_PLLRDY ((uint8_t)0x10)
<01>
RCC_IT_PLLI2SRDY ((uint8_t)0x20)
<01>
RCC_IT_PLLSAIRDY ((uint8_t)0x40)
<01>
RCC_IT_CSS ((uint8_t)0x80)
<01>
IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
<01>
IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_PLLSAIRDY) || ((IT) == RCC_IT_PLLI2SRDY))
<01>
IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
<01>
RCC_LSE_OFF ((uint8_t)0x00)
<01>
RCC_LSE_ON ((uint8_t)0x01)
<01>
RCC_LSE_Bypass ((uint8_t)0x04)
<01>
IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_O
..\FWLIB\inc\stm32f4xx_rcc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>SYSCLK_FrequencyY
#HCLK_FrequencyY
#PCLK1_FrequencyY
#PCLK2_FrequencyY
#PRCC_ClocksTypeDef<12>
6
_`a

__STM32F4xx_RTC_H &
<01>
RTC_HourFormat_24 ((uint32_t)0x00000000)
<01>
RTC_HourFormat_12 ((uint32_t)0x00000040)
<01>
IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || ((FORMAT) == RTC_HourFormat_24))
<01>
IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
<01>
IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
<01>
IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
<01>
IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
<01>
IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
<01>
IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
<01>
RTC_H12_AM ((uint8_t)0x00)
<01>
RTC_H12_PM ((uint8_t)0x40)
<01>
IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
<01>
IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
<01>
RTC_Month_January ((uint8_t)0x01)
<01>
RTC_Month_February ((uint8_t)0x02)
<01>
RTC_Month_March ((uint8_t)0x03)
<01>
RTC_Month_April ((uint8_t)0x04)
<01>
RTC_Month_May ((uint8_t)0x05)
<01>
RTC_Month_June ((uint8_t)0x06)
<01>
RTC_Month_July ((uint8_t)0x07)
<01>
RTC_Month_August ((uint8_t)0x08)
<01>
RTC_Month_September ((uint8_t)0x09)
<01>
RTC_Month_October ((uint8_t)0x10)
<01>
RTC_Month_November ((uint8_t)0x11)
<01>
RTC_Month_December ((uint8_t)0x12)
<01>
IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
<01>
IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
<01>
RTC_Weekday_Monday ((uint8_t)0x01)
<01>
RTC_Weekday_Tuesday ((uint8_t)0x02)
<01>
RTC_Weekday_Wednesday ((uint8_t)0x03)
<01>
RTC_Weekday_Thursday ((uint8_t)0x04)
<01>
RTC_Weekday_Friday ((uint8_t)0x05)
<01>
RTC_Weekday_Saturday ((uint8_t)0x06)
<01>
RTC_Weekday_Sunday ((uint8_t)0x07)
<01>
IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || ((WEEKDAY) == RTC_Weekday_Tuesday) || ((WEEKDAY) == RTC_Weekday_Wednesday) || ((WEEKDAY) == RTC_Weekday_Thursday) || ((WEEKDAY) == RTC_Weekday_Friday) || ((WEEKDAY) == RTC_Weekday_Saturday) || ((WEEKDAY) == RTC_Weekday_Sunday))
<01>
IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
<01>
IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || ((WEEKDAY) == RTC_Weekday_Tuesday) || ((WEEKDAY) == RTC_Weekday_Wednesday) || ((WEEKDAY) == RTC_Weekday_Thursday) || ((WEEKDAY) == RTC_Weekday_Friday) || ((WEEKDAY) == RTC_Weekday_Saturday) || ((WEEKDAY) == RTC_Weekday_Sunday))
<01>RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
<01>RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
<01>IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
<01>RTC_AlarmMask_None ((uint32_t)0x00000000)
<01>RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
<01>RTC_AlarmMask_Hours ((uint32_t)0x00800000)
<01>RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
<01>RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
<01>RTC_AlarmMask_All ((uint32_t)0x80808080)
<01>IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
<01>RTC_Alarm_A ((uint32_t)0x00000100)
<01>RTC_Alarm_B ((uint32_t)0x00000200)
<01>IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
<01>IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
<01>RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000)
<01>RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000)
<01>RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000)
<01>RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000)
<01>RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000)
<01>RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000)
<01>RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000)
<01>RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000)
<01>RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000)
<01>RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000)
<01>RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000)
<01>RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000)
<01>RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000)
<01>RTC_AlarmSubSecondMask_SS14_13 ((uint32
..\FWLIB\inc\stm32f4xx_rtc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>RTC_HourFormatY
#RTC_AsynchPredivY
#RTC_SynchPredivY
#PRTC_InitTypeDef<12>
?*<2A>RTC_Hours:
#RTC_Minutes:
#
RTC_Seconds:
#RTC_H12:
#PRTC_TimeTypeDef*

S*<2A>RTC_WeekDay:
#RTC_Month:
#
RTC_Date:
#RTC_Year:
#PRTC_DateTypeDef<12>

e*<2A>RTC_AlarmTime}
#RTC_AlarmMaskY
#RTC_AlarmDateWeekDaySelY
#RTC_AlarmDateWeekDay:
#PRTC_AlarmTypeDef<12>

y
cde

__STM32F4xx_SDIO_H &
~SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
<01>
IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || ((EDGE) == SDIO_ClockEdge_Falling))
<01>
SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
<01>
SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
<01>
IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || ((BYPASS) == SDIO_ClockBypass_Enable))
<01>
SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
<01>
SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
<01>
IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || ((SAVE) == SDIO_ClockPowerSave_Enable))
<01>
SDIO_BusWide_1b ((uint32_t)0x00000000)
<01>
SDIO_BusWide_4b ((uint32_t)0x00000800)
<01>
SDIO_BusWide_8b ((uint32_t)0x00001000)
<01>
IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || ((WIDE) == SDIO_BusWide_8b))
<01>
SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
<01>
SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
<01>
IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || ((CONTROL) == SDIO_HardwareFlowControl_Enable))
<01>
SDIO_PowerState_OFF ((uint32_t)0x00000000)
<01>
SDIO_PowerState_ON ((uint32_t)0x00000003)
<01>
IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
<01>
SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
<01>
SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
<01>
SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
<01>
SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
<01>
SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
<01>
SDIO_IT_RXOVERR ((uint32_t)0x00000020)
<01>
SDIO_IT_CMDREND ((uint32_t)0x00000040)
<01>
SDIO_IT_CMDSENT ((uint32_t)0x00000080)
<01>
SDIO_IT_DATAEND ((uint32_t)0x00000100)
<01>
SDIO_IT_STBITERR ((uint32_t)0x00000200)
<01>
SDIO_IT_DBCKEND ((uint32_t)0x00000400)
<01>
SDIO_IT_CMDACT ((uint32_t)0x00000800)
<01>
SDIO_IT_TXACT ((uint32_t)0x00001000)
<01>
SDIO_IT_RXACT ((uint32_t)0x00002000)
<01>
SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
<01>
SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
<01>
SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
<01>
SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
<01>
SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
<01>
SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
<01>
SDIO_IT_TXDAVL ((uint32_t)0x00100000)
<01>
SDIO_IT_RXDAVL ((uint32_t)0x00200000)
<01>
SDIO_IT_SDIOIT ((uint32_t)0x00400000)
<01>
SDIO_IT_CEATAEND ((uint32_t)0x00800000)
<01>
IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
<01>
IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
<01>
SDIO_Response_No ((uint32_t)0x00000000)
<01>
SDIO_Response_Short ((uint32_t)0x00000040)
<01>
SDIO_Response_Long ((uint32_t)0x000000C0)
<01>
IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || ((RESPONSE) == SDIO_Response_Short) || ((RESPONSE) == SDIO_Response_Long))
<01>SDIO_Wait_No ((uint32_t)0x00000000)
<01>SDIO_Wait_IT ((uint32_t)0x00000100)
<01>SDIO_Wait_Pend ((uint32_t)0x00000200)
<01>IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || ((WAIT) == SDIO_Wait_Pend))
<01>SDIO_CPSM_Disable ((uint32_t)0x00000000)
<01>SDIO_CPSM_Enable ((uint32_t)0x00000400)
<01>IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
<01>SDIO_RESP1 ((uint32_t)0x00000000)
<01>SDIO_RESP2 ((uint32_t)0x00000004)
<01>SDIO_RESP3 ((uint32_t)0x00000008)
<01>SDIO_RESP4 ((uint32_t)0x0000000C)
<01>IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_R
..\FWLIB\inc\stm32f4xx_sdio.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>SDIO_ClockEdgeY
#SDIO_ClockBypassY
#SDIO_ClockPowerSaveY
#SDIO_BusWideY
#SDIO_HardwareFlowControlY
#SDIO_ClockDiv:
#PSDIO_InitTypeDef<12>
H*<2A>SDIO_ArgumentY
#SDIO_CmdIndexY
#SDIO_ResponseY
#SDIO_WaitY
#SDIO_CPSMY
#PSDIO_CmdInitTypeDef

\*<2A>SDIO_DataTimeOutY
#SDIO_DataLengthY
#SDIO_DataBlockSizeY
#SDIO_TransferDirY
#SDIO_TransferModeY
#SDIO_DPSMY
#PSDIO_DataInitTypeDef

q
ghi

__STM32F4xx_SPI_H &
wIS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3) || ((PERIPH) == SPI4) || ((PERIPH) == SPI5) || ((PERIPH) == SPI6))
~IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || ((PERIPH) == SPI2) || ((PERIPH) == SPI3) || ((PERIPH) == SPI4) || ((PERIPH) == SPI5) || ((PERIPH) == SPI6) || ((PERIPH) == I2S2ext) || ((PERIPH) == I2S3ext))
<01>
IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3))
<01>
IS_SPI_23_PERIPH_EXT(PERIPH) (((PERIPH) == SPI2) || ((PERIPH) == SPI3) || ((PERIPH) == I2S2ext) || ((PERIPH) == I2S3ext))
<01>
IS_I2S_EXT_PERIPH(PERIPH) (((PERIPH) == I2S2ext) || ((PERIPH) == I2S3ext))
<01>
SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
<01>
SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
<01>
SPI_Direction_1Line_Rx ((uint16_t)0x8000)
<01>
SPI_Direction_1Line_Tx ((uint16_t)0xC000)
<01>
IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || ((MODE) == SPI_Direction_2Lines_RxOnly) || ((MODE) == SPI_Direction_1Line_Rx) || ((MODE) == SPI_Direction_1Line_Tx))
<01>
SPI_Mode_Master ((uint16_t)0x0104)
<01>
SPI_Mode_Slave ((uint16_t)0x0000)
<01>
IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || ((MODE) == SPI_Mode_Slave))
<01>
SPI_DataSize_16b ((uint16_t)0x0800)
<01>
SPI_DataSize_8b ((uint16_t)0x0000)
<01>
IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || ((DATASIZE) == SPI_DataSize_8b))
<01>
SPI_CPOL_Low ((uint16_t)0x0000)
<01>
SPI_CPOL_High ((uint16_t)0x0002)
<01>
IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || ((CPOL) == SPI_CPOL_High))
<01>
SPI_CPHA_1Edge ((uint16_t)0x0000)
<01>
SPI_CPHA_2Edge ((uint16_t)0x0001)
<01>
IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || ((CPHA) == SPI_CPHA_2Edge))
<01>
SPI_NSS_Soft ((uint16_t)0x0200)
<01>
SPI_NSS_Hard ((uint16_t)0x0000)
<01>
IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || ((NSS) == SPI_NSS_Hard))
<01>
SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
<01>
SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
<01>
SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
<01>
SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
<01>
SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
<01>
SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
<01>
SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
<01>
SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
<01>
IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || ((PRESCALER) == SPI_BaudRatePrescaler_4) || ((PRESCALER) == SPI_BaudRatePrescaler_8) || ((PRESCALER) == SPI_BaudRatePrescaler_16) || ((PRESCALER) == SPI_BaudRatePrescaler_32) || ((PRESCALER) == SPI_BaudRatePrescaler_64) || ((PRESCALER) == SPI_BaudRatePrescaler_128) || ((PRESCALER) == SPI_BaudRatePrescaler_256))
<01>
SPI_FirstBit_MSB ((uint16_t)0x0000)
<01>
SPI_FirstBit_LSB ((uint16_t)0x0080)
<01>
IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || ((BIT) == SPI_FirstBit_LSB))
<01>I2S_Mode_SlaveTx ((uint16_t)0x0000)
<01>I2S_Mode_SlaveRx ((uint16_t)0x0100)
<01>I2S_Mode_MasterTx ((uint16_t)0x0200)
<01>I2S_Mode_MasterRx ((uint16_t)0x0300)
<01>IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || ((MODE) == I2S_Mode_SlaveRx) || ((MODE) == I2S_Mode_MasterTx)|| ((MODE) == I2S_Mode_MasterRx))
<01>I2S_Standard_Phillips ((uint16_t)0x0000)
<01>I2S_Standard_MSB ((uint16_t)0x0010)
<01>I2S_Standard_LSB ((uint16_t)0x0020)
<01>I2S_Standard_PCMShort ((uint16_t)0x0030)
<01>I2S_Standard_PCMLong ((uint16_t)0x00B0)
<01>IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || ((STANDARD) == I2S_Standard_MSB) || ((STANDARD) == I2S_Standard_LSB) || ((STANDARD) == I2S_Standard_PCMShort) || ((STANDARD) == I2S_Standard_PCMLong))
<01>I2S_DataFormat_16b ((uint16_t)0x0000)
<01>I2S_DataFormat_16bextended ((uint16_t)0x0001)
<01>I2S_DataFormat_24b ((uint16_t)0x0003)
<01>I2S_DataFormat_32b ((uint16_t)0x0005)
<01>IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || ((FORMAT) == I2S_DataFormat_16bextended) || ((FORMAT) == I2S_DataFormat_24b) || ((FORMAT) == I2S_DataFormat_32b))
<01>I2S_MCLKOutput_Enable ((uint16_t)0x0200)
<01>I2S_MCLKOutput_Disable ((uint16_t)0x0000)
<01>IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || ((OUTPUT) == I2S_MCLKOutput_Disable))
<01>I2S_A
..\FWLIB\inc\stm32f4xx_spi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>SPI_DirectionI
#SPI_ModeI
#SPI_DataSizeI
#SPI_CPOLI
#SPI_CPHAI
#SPI_NSSI
#
SPI_BaudRatePrescalerI
#SPI_FirstBitI
#SPI_CRCPolynomialI
#PSPI_InitTypeDef<12>
U*<2A>I2S_ModeI
#I2S_StandardI
#I2S_DataFormatI
#I2S_MCLKOutputI
#I2S_AudioFreqY
#I2S_CPOLI
#PI2S_InitTypeDef<12>

o
klm

__STM32F4xx_SYSCFG_H &
:EXTI_PortSourceGPIOA ((uint8_t)0x00)
;EXTI_PortSourceGPIOB ((uint8_t)0x01)
<EXTI_PortSourceGPIOC ((uint8_t)0x02)
=EXTI_PortSourceGPIOD ((uint8_t)0x03)
>EXTI_PortSourceGPIOE ((uint8_t)0x04)
?EXTI_PortSourceGPIOF ((uint8_t)0x05)
@EXTI_PortSourceGPIOG ((uint8_t)0x06)
AEXTI_PortSourceGPIOH ((uint8_t)0x07)
BEXTI_PortSourceGPIOI ((uint8_t)0x08)
CEXTI_PortSourceGPIOJ ((uint8_t)0x09)
DEXTI_PortSourceGPIOK ((uint8_t)0x0A)
FIS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || ((PORTSOURCE) == EXTI_PortSourceGPIOB) || ((PORTSOURCE) == EXTI_PortSourceGPIOC) || ((PORTSOURCE) == EXTI_PortSourceGPIOD) || ((PORTSOURCE) == EXTI_PortSourceGPIOE) || ((PORTSOURCE) == EXTI_PortSourceGPIOF) || ((PORTSOURCE) == EXTI_PortSourceGPIOG) || ((PORTSOURCE) == EXTI_PortSourceGPIOH) || ((PORTSOURCE) == EXTI_PortSourceGPIOI) || ((PORTSOURCE) == EXTI_PortSourceGPIOJ) || ((PORTSOURCE) == EXTI_PortSourceGPIOK))
ZEXTI_PinSource0 ((uint8_t)0x00)
[EXTI_PinSource1 ((uint8_t)0x01)
\EXTI_PinSource2 ((uint8_t)0x02)
]EXTI_PinSource3 ((uint8_t)0x03)
^EXTI_PinSource4 ((uint8_t)0x04)
_EXTI_PinSource5 ((uint8_t)0x05)
`EXTI_PinSource6 ((uint8_t)0x06)
aEXTI_PinSource7 ((uint8_t)0x07)
bEXTI_PinSource8 ((uint8_t)0x08)
cEXTI_PinSource9 ((uint8_t)0x09)
dEXTI_PinSource10 ((uint8_t)0x0A)
eEXTI_PinSource11 ((uint8_t)0x0B)
fEXTI_PinSource12 ((uint8_t)0x0C)
gEXTI_PinSource13 ((uint8_t)0x0D)
hEXTI_PinSource14 ((uint8_t)0x0E)
iEXTI_PinSource15 ((uint8_t)0x0F)
jIS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || ((PINSOURCE) == EXTI_PinSource1) || ((PINSOURCE) == EXTI_PinSource2) || ((PINSOURCE) == EXTI_PinSource3) || ((PINSOURCE) == EXTI_PinSource4) || ((PINSOURCE) == EXTI_PinSource5) || ((PINSOURCE) == EXTI_PinSource6) || ((PINSOURCE) == EXTI_PinSource7) || ((PINSOURCE) == EXTI_PinSource8) || ((PINSOURCE) == EXTI_PinSource9) || ((PINSOURCE) == EXTI_PinSource10) || ((PINSOURCE) == EXTI_PinSource11) || ((PINSOURCE) == EXTI_PinSource12) || ((PINSOURCE) == EXTI_PinSource13) || ((PINSOURCE) == EXTI_PinSource14) || ((PINSOURCE) == EXTI_PinSource15))
<01>
SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
<01>
SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
<01>
SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
<01>
SYSCFG_MemoryRemap_SDRAM ((uint8_t)0x04)
<01>
SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
<01>
IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || ((REMAP) == SYSCFG_MemoryRemap_SRAM) || ((REMAP) == SYSCFG_MemoryRemap_FSMC))
<01>
SYSCFG_ETH_MediaInterface_MII ((uint32_t)0x00000000)
<01>
SYSCFG_ETH_MediaInterface_RMII ((uint32_t)0x00000001)
<01>
IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))XO






..\FWLIB\inc\..\USER\stm32f4xx_syscfg.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_syscfg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
opq

__STM32F4xx_TIM_H &
<01>
IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM10) || ((PERIPH) == TIM11) || ((PERIPH) == TIM12) || (((PERIPH) == TIM13) || ((PERIPH) == TIM14)))
<01>
IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM10) || ((PERIPH) == TIM11) || ((PERIPH) == TIM12) || ((PERIPH) == TIM13) || ((PERIPH) == TIM14))
<01>
IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8) || ((PERIPH) == TIM9) || ((PERIPH) == TIM12))
<01>
IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM8))
<01>
IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM8))
<01>
IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || ((PERIPH) == TIM2) || ((PERIPH) == TIM3) || ((PERIPH) == TIM4) || ((PERIPH) == TIM5) || ((PERIPH) == TIM6) || ((PERIPH) == TIM7) || ((PERIPH) == TIM8))
<01>
IS_TIM_LIST6_PERIPH(TIMx) (((TIMx) == TIM2) || ((TIMx) == TIM5) || ((TIMx) == TIM11))
<01>
TIM_OCMode_Timing ((uint16_t)0x0000)
<01>
TIM_OCMode_Active ((uint16_t)0x0010)
<01>
TIM_OCMode_Inactive ((uint16_t)0x0020)
<01>
TIM_OCMode_Toggle ((uint16_t)0x0030)
<01>
TIM_OCMode_PWM1 ((uint16_t)0x0060)
<01>
TIM_OCMode_PWM2 ((uint16_t)0x0070)
<01>
IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2))
<01>
IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || ((MODE) == TIM_OCMode_Active) || ((MODE) == TIM_OCMode_Inactive) || ((MODE) == TIM_OCMode_Toggle)|| ((MODE) == TIM_OCMode_PWM1) || ((MODE) == TIM_OCMode_PWM2) || ((MODE) == TIM_ForcedAction_Active) || ((MODE) == TIM_ForcedAction_InActive))
<01>TIM_OPMode_Single ((uint16_t)0x0008)
<01>TIM_OPMode_Repetitive ((uint16_t)0x0000)
<01>IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || ((MODE) == TIM_OPMode_Repetitive))
<01>TIM_Channel_1 ((uint16_t)0x0000)
<01>TIM_Channel_2 ((uint16_t)0x0004)
<01>TIM_Channel_3 ((uint16_t)0x0008)
<01>TIM_Channel_4 ((uint16_t)0x000C)
<01>IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3) || ((CHANNEL) == TIM_Channel_4))
<01>IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2))
<01>IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || ((CHANNEL) == TIM_Channel_2) || ((CHANNEL) == TIM_Channel_3))
<01>TIM_CKD_DIV1 ((uint16_t)0x0000)
<01>TIM_CKD_DIV2 ((uint16_t)0x0100)
<01>TIM_CKD_DIV4 ((uint16_t)0x0200)
<01>IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || ((DIV) == TIM_CKD_DIV2) || ((DIV) == TIM_CKD_DIV4))
<01>TIM_CounterMode_Up ((uint16_t)0x0000)
<01>TIM_CounterMode_Down ((uint16_t)0x0010)
<01>TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
<01>TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
<01>TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
<01>IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || ((MODE) == TIM_CounterMode_Down) || ((MODE) == TIM_CounterMode_CenterAligned1) || ((MODE) == TIM_CounterMode_CenterAligned2) || ((MODE) == TIM_CounterMode_CenterAligned3))
<01>TIM_OCPolarity_High ((uint16_t)0x0000)
<01>TIM_OCPolarity_Low ((uint16_t)0x0002)
<01>IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || ((POLARITY) == TIM_OCPolarity_Low))
<01>TIM_OCNPolarity_High ((uint16_t)0x0000)
<01>TIM_OCNPolarity_Low ((uint16_t)0x0008)
<01>IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarit
..\FWLIB\inc\stm32f4xx_tim.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>TIM_PrescalerI
#TIM_CounterModeI
#TIM_PeriodY
#TIM_ClockDivisionI
#TIM_RepetitionCounter:
#
PTIM_TimeBaseInitTypeDef<12>
N*<2A>TIM_OCModeI
#TIM_OutputStateI
#TIM_OutputNStateI
#TIM_PulseY
#TIM_OCPolarityI
#TIM_OCNPolarityI
#TIM_OCIdleStateI
#TIM_OCNIdleStateI
#PTIM_OCInitTypeDefe

q*<2A>
TIM_ChannelI
#TIM_ICPolarityI
#TIM_ICSelectionI
#TIM_ICPrescalerI
#TIM_ICFilterI
#PTIM_ICInitTypeDefA
<01>
*<2A>TIM_OSSRStateI
#TIM_OSSIStateI
#TIM_LOCKLevelI
#TIM_DeadTimeI
#TIM_BreakI
#TIM_BreakPolarityI
#
TIM_AutomaticOutputI
#PTIM_BDTRInitTypeDef<12>
<01>

stu

__STM32F4xx_USART_H &
nIS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == UART4) || ((PERIPH) == UART5) || ((PERIPH) == USART6) || ((PERIPH) == UART7) || ((PERIPH) == UART8))
wIS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || ((PERIPH) == USART2) || ((PERIPH) == USART3) || ((PERIPH) == USART6))
<01>
USART_WordLength_8b ((uint16_t)0x0000)
<01>
USART_WordLength_9b ((uint16_t)0x1000)
<01>
IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || ((LENGTH) == USART_WordLength_9b))
<01>
USART_StopBits_1 ((uint16_t)0x0000)
<01>
USART_StopBits_0_5 ((uint16_t)0x1000)
<01>
USART_StopBits_2 ((uint16_t)0x2000)
<01>
USART_StopBits_1_5 ((uint16_t)0x3000)
<01>
IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || ((STOPBITS) == USART_StopBits_0_5) || ((STOPBITS) == USART_StopBits_2) || ((STOPBITS) == USART_StopBits_1_5))
<01>
USART_Parity_No ((uint16_t)0x0000)
<01>
USART_Parity_Even ((uint16_t)0x0400)
<01>
USART_Parity_Odd ((uint16_t)0x0600)
<01>
IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || ((PARITY) == USART_Parity_Even) || ((PARITY) == USART_Parity_Odd))
<01>
USART_Mode_Rx ((uint16_t)0x0004)
<01>
USART_Mode_Tx ((uint16_t)0x0008)
<01>
IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
<01>
USART_HardwareFlowControl_None ((uint16_t)0x0000)
<01>
USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
<01>
USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
<01>
USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
<01>
IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == USART_HardwareFlowControl_None) || ((CONTROL) == USART_HardwareFlowControl_RTS) || ((CONTROL) == USART_HardwareFlowControl_CTS) || ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
<01>
USART_Clock_Disable ((uint16_t)0x0000)
<01>
USART_Clock_Enable ((uint16_t)0x0800)
<01>
IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || ((CLOCK) == USART_Clock_Enable))
<01>
USART_CPOL_Low ((uint16_t)0x0000)
<01>
USART_CPOL_High ((uint16_t)0x0400)
<01>
IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
<01>
USART_CPHA_1Edge ((uint16_t)0x0000)
<01>
USART_CPHA_2Edge ((uint16_t)0x0200)
<01>
IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
<01>
USART_LastBit_Disable ((uint16_t)0x0000)
<01>
USART_LastBit_Enable ((uint16_t)0x0100)
<01>
IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || ((LASTBIT) == USART_LastBit_Enable))
<01>
USART_IT_PE ((uint16_t)0x0028)
<01>
USART_IT_TXE ((uint16_t)0x0727)
<01>
USART_IT_TC ((uint16_t)0x0626)
<01>
USART_IT_RXNE ((uint16_t)0x0525)
<01>
USART_IT_ORE_RX ((uint16_t)0x0325)
<01>
USART_IT_IDLE ((uint16_t)0x0424)
<01>
USART_IT_LBD ((uint16_t)0x0846)
<01>
USART_IT_CTS ((uint16_t)0x096A)
<01>
USART_IT_ERR ((uint16_t)0x0060)
<01>
USART_IT_ORE_ER ((uint16_t)0x0360)
<01>
USART_IT_NE ((uint16_t)0x0260)
<01>USART_IT_FE ((uint16_t)0x0160)
<01>USART_IT_ORE USART_IT_ORE_ER
<01>IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
<01>IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || ((IT) == USART_IT_ORE_RX) || ((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
<01>IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
<01>USART_DMAReq_Tx ((uint16_t)0x0080)
<01>USART_DMAReq_Rx ((uint16_t)0x0040)
<01>IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
<01>USART_WakeUp_IdleLine ((uint16_t)0x0000)
<01>USART_WakeUp_AddressMark ((uint16_t)0x0800)
<01>IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || ((WAKEUP) == USART_WakeUp_AddressMark))
<01>USART_LINBreakDetectLength_1
..\FWLIB\inc\stm32f4xx_usart.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>USART_BaudRateY
#USART_WordLengthI
#USART_StopBitsI
#USART_ParityI
#USART_ModeI
#
USART_HardwareFlowControlI
#PUSART_InitTypeDef<12>
Q*<2A>USART_ClockI
#USART_CPOLI
#USART_CPHAI
#USART_LastBitI
#PUSART_ClockInitTypeDefz

f
wxy

__STM32F4xx_WWDG_H &
;WWDG_Prescaler_1 ((uint32_t)0x00000000)
<WWDG_Prescaler_2 ((uint32_t)0x00000080)
=WWDG_Prescaler_4 ((uint32_t)0x00000100)
>WWDG_Prescaler_8 ((uint32_t)0x00000180)
?IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || ((PRESCALER) == WWDG_Prescaler_2) || ((PRESCALER) == WWDG_Prescaler_4) || ((PRESCALER) == WWDG_Prescaler_8))
CIS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
DIS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))XM






..\FWLIB\inc\..\USER\stm32f4xx_wwdg.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_wwdg.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
{|}

__MISC_H &
VNVIC_VectTab_RAM ((uint32_t)0x20000000)
WNVIC_VectTab_FLASH ((uint32_t)0x08000000)
XIS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || ((VECTTAB) == NVIC_VectTab_FLASH))
bNVIC_LP_SEVONPEND ((uint8_t)0x10)
cNVIC_LP_SLEEPDEEP ((uint8_t)0x04)
dNVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
eIS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || ((LP) == NVIC_LP_SLEEPDEEP) || ((LP) == NVIC_LP_SLEEPONEXIT))
pNVIC_PriorityGroup_0 ((uint32_t)0x700)
rNVIC_PriorityGroup_1 ((uint32_t)0x600)
tNVIC_PriorityGroup_2 ((uint32_t)0x500)
vNVIC_PriorityGroup_3 ((uint32_t)0x400)
xNVIC_PriorityGroup_4 ((uint32_t)0x300)
{IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || ((GROUP) == NVIC_PriorityGroup_1) || ((GROUP) == NVIC_PriorityGroup_2) || ((GROUP) == NVIC_PriorityGroup_3) || ((GROUP) == NVIC_PriorityGroup_4))
<01>
IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<01>
IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
<01>
IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
<01>
SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
<01>
SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
<01>
IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || ((SOURCE) == SysTick_CLKSource_HCLK_Div8))LC






..\FWLIB\inc\..\USER\misc.h
stm32f4xx.h

\

..\FWLIB\inc\misc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>NVIC_IRQChannel:
#NVIC_IRQChannelPreemptionPriority:
#
NVIC_IRQChannelSubPriority:
#NVIC_IRQChannelCmd<10>#PNVIC_InitTypeDef<12>
J
<00><00>

__STM32F4xx_CRYP_H &
CRYP_AlgoDir_Encrypt ((uint16_t)0x0000)
<01>
CRYP_AlgoDir_Decrypt ((uint16_t)0x0004)
<01>
IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || ((ALGODIR) == CRYP_AlgoDir_Decrypt))
<01>
CRYP_AlgoMode_TDES_ECB ((uint32_t)0x00000000)
<01>
CRYP_AlgoMode_TDES_CBC ((uint32_t)0x00000008)
<01>
CRYP_AlgoMode_DES_ECB ((uint32_t)0x00000010)
<01>
CRYP_AlgoMode_DES_CBC ((uint32_t)0x00000018)
<01>
CRYP_AlgoMode_AES_ECB ((uint32_t)0x00000020)
<01>
CRYP_AlgoMode_AES_CBC ((uint32_t)0x00000028)
<01>
CRYP_AlgoMode_AES_CTR ((uint32_t)0x00000030)
<01>
CRYP_AlgoMode_AES_Key ((uint32_t)0x00000038)
<01>
CRYP_AlgoMode_AES_GCM ((uint32_t)0x00080000)
<01>
CRYP_AlgoMode_AES_CCM ((uint32_t)0x00080008)
<01>
IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| ((ALGOMODE) == CRYP_AlgoMode_DES_ECB) || ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || ((ALGOMODE) == CRYP_AlgoMode_AES_Key) || ((ALGOMODE) == CRYP_AlgoMode_AES_GCM) || ((ALGOMODE) == CRYP_AlgoMode_AES_CCM))
<01>
CRYP_Phase_Init ((uint32_t)0x00000000)
<01>
CRYP_Phase_Header CRYP_CR_GCM_CCMPH_0
<01>
CRYP_Phase_Payload CRYP_CR_GCM_CCMPH_1
<01>
CRYP_Phase_Final CRYP_CR_GCM_CCMPH
<01>
IS_CRYP_PHASE(PHASE) (((PHASE) == CRYP_Phase_Init) || ((PHASE) == CRYP_Phase_Header) || ((PHASE) == CRYP_Phase_Payload) || ((PHASE) == CRYP_Phase_Final))
<01>
CRYP_DataType_32b ((uint16_t)0x0000)
<01>
CRYP_DataType_16b ((uint16_t)0x0040)
<01>
CRYP_DataType_8b ((uint16_t)0x0080)
<01>
CRYP_DataType_1b ((uint16_t)0x00C0)
<01>
IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || ((DATATYPE) == CRYP_DataType_16b)|| ((DATATYPE) == CRYP_DataType_8b)|| ((DATATYPE) == CRYP_DataType_1b))
<01>
CRYP_KeySize_128b ((uint16_t)0x0000)
<01>
CRYP_KeySize_192b ((uint16_t)0x0100)
<01>
CRYP_KeySize_256b ((uint16_t)0x0200)
<01>
IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| ((KEYSIZE) == CRYP_KeySize_192b)|| ((KEYSIZE) == CRYP_KeySize_256b))
<01>
CRYP_FLAG_BUSY ((uint8_t)0x10)
<01>
CRYP_FLAG_IFEM ((uint8_t)0x01)
<01>
CRYP_FLAG_IFNF ((uint8_t)0x02)
<01>
CRYP_FLAG_INRIS ((uint8_t)0x22)
<01>
CRYP_FLAG_OFNE ((uint8_t)0x04)
<01>
CRYP_FLAG_OFFU ((uint8_t)0x08)
<01>
CRYP_FLAG_OUTRIS ((uint8_t)0x21)
<01>
IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM) || ((FLAG) == CRYP_FLAG_IFNF) || ((FLAG) == CRYP_FLAG_OFNE) || ((FLAG) == CRYP_FLAG_OFFU) || ((FLAG) == CRYP_FLAG_BUSY) || ((FLAG) == CRYP_FLAG_OUTRIS)|| ((FLAG) == CRYP_FLAG_INRIS))
<01>
CRYP_IT_INI ((uint8_t)0x01)
<01>
CRYP_IT_OUTI ((uint8_t)0x02)
<01>
IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
<01>
IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
<01>MODE_ENCRYPT ((uint8_t)0x01)
<01>MODE_DECRYPT ((uint8_t)0x00)
<01>CRYP_DMAReq_DataIN ((uint8_t)0x01)
<01>CRYP_DMAReq_DataOUT ((uint8_t)0x02)
<01>IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))XM






..\FWLIB\inc\..\USER\stm32f4xx_cryp.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_cryp.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>CRYP_AlgoDirY
#CRYP_AlgoModeY
#CRYP_DataTypeY
#CRYP_KeySizeY
#PCRYP_InitTypeDef<12>
A*<2A> CRYP_Key0LeftY
#CRYP_Key0RightY
#CRYP_Key1LeftY
#CRYP_Key1RightY
#CRYP_Key2LeftY
#CRYP_Key2RightY
#CRYP_Key3LeftY
#CRYP_Key3RightY
#PCRYP_KeyInitTypeDef;

P*<2A>CRYP_IV0LeftY
#CRYP_IV0RightY
#CRYP_IV1LeftY
#CRYP_IV1RightY
#PCRYP_IVInitTypeDef
Z*<2A>tCR_CurrentConfigY
#CRYP_IV0LRY
#CRYP_IV0RRY
#CRYP_IV1LRY
#CRYP_IV1RRY
#CRYP_K0LRY
#CRYP_K0RRY
#CRYP_K1LRY
#CRYP_K1RRY
# CRYP_K2LRY
#$CRYP_K2RRY
#(CRYP_K3LRY
#,CRYP_K3RRY
#0<03>Y

CRYP_CSGCMCCMR<12>#4<03>Y

CRYP_CSGCMR<12>#TPCRYP_Context<12>
s
<00><00><00>

__STM32F4xx_HASH_H &
aHASH_AlgoSelection_SHA1 ((uint32_t)0x0000)
bHASH_AlgoSelection_SHA224 HASH_CR_ALGO_1
cHASH_AlgoSelection_SHA256 HASH_CR_ALGO
dHASH_AlgoSelection_MD5 HASH_CR_ALGO_0
fIS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
qHASH_AlgoMode_HASH ((uint32_t)0x00000000)
rHASH_AlgoMode_HMAC HASH_CR_MODE
tIS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || ((ALGOMODE) == HASH_AlgoMode_HMAC))
}HASH_DataType_32b ((uint32_t)0x0000)
~HASH_DataType_16b HASH_CR_DATATYPE_0
HASH_DataType_8b HASH_CR_DATATYPE_1
<01>
HASH_DataType_1b HASH_CR_DATATYPE
<01>
IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| ((DATATYPE) == HASH_DataType_16b)|| ((DATATYPE) == HASH_DataType_8b) || ((DATATYPE) == HASH_DataType_1b))
<01>
HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000)
<01>
HASH_HMACKeyType_LongKey HASH_CR_LKEY
<01>
IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || ((KEYTYPE) == HASH_HMACKeyType_LongKey))
<01>
IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
<01>
HASH_IT_DINI HASH_IMR_DINIM
<01>
HASH_IT_DCI HASH_IMR_DCIM
<01>
IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
<01>
IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
<01>
HASH_FLAG_DINIS HASH_SR_DINIS
<01>
HASH_FLAG_DCIS HASH_SR_DCIS
<01>
HASH_FLAG_DMAS HASH_SR_DMAS
<01>
HASH_FLAG_BUSY HASH_SR_BUSY
<01>
HASH_FLAG_DINNE HASH_CR_DINNE
<01>
IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || ((FLAG) == HASH_FLAG_DCIS) || ((FLAG) == HASH_FLAG_DMAS) || ((FLAG) == HASH_FLAG_BUSY) || ((FLAG) == HASH_FLAG_DINNE))
<01>
IS_HASH_CLEAR_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || ((FLAG) == HASH_FLAG_DCIS))XM






..\FWLIB\inc\..\USER\stm32f4xx_hash.h
stm32f4xx.h

<01>

..\FWLIB\inc\stm32f4xx_hash.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>HASH_AlgoSelectionY
#HASH_AlgoModeY
#HASH_DataTypeY
#HASH_HMACKeyTypeY
#PHASH_InitTypeDef<12>
@*<2A> <03>Y

DataI
#PHASH_MsgDigestE

K*<2A><03>
HASH_IMRY
#HASH_STRY
#HASH_CRY
#<03>Y

5HASH_CSR<12>
#PHASH_Contextw

V
<00><00><00>

__STM32F4xx_RNG_H &
:RNG_FLAG_DRDY ((uint8_t)0x0001)
;RNG_FLAG_CECS ((uint8_t)0x0002)
<RNG_FLAG_SECS ((uint8_t)0x0004)
>IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || ((RNG_FLAG) == RNG_FLAG_CECS) || ((RNG_FLAG) == RNG_FLAG_SECS))
AIS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || ((RNG_FLAG) == RNG_FLAG_SECS))
JRNG_IT_CEI ((uint8_t)0x20)
KRNG_IT_SEI ((uint8_t)0x40)
MIS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
NIS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))XL






..\FWLIB\inc\..\USER\stm32f4xx_rng.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_rng.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER
<00><00><00>

__STM32F4xx_CAN_H &
2IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || ((PERIPH) == CAN2))
<01>
CAN_InitStatus_Failed ((uint8_t)0x00)
<01>
CAN_InitStatus_Success ((uint8_t)0x01)
<01>
CANINITFAILED CAN_InitStatus_Failed
<01>
CANINITOK CAN_InitStatus_Success
<01>
CAN_Mode_Normal ((uint8_t)0x00)
<01>
CAN_Mode_LoopBack ((uint8_t)0x01)
<01>
CAN_Mode_Silent ((uint8_t)0x02)
<01>
CAN_Mode_Silent_LoopBack ((uint8_t)0x03)
<01>
IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || ((MODE) == CAN_Mode_LoopBack)|| ((MODE) == CAN_Mode_Silent) || ((MODE) == CAN_Mode_Silent_LoopBack))
<01>
CAN_OperatingMode_Initialization ((uint8_t)0x00)
<01>
CAN_OperatingMode_Normal ((uint8_t)0x01)
<01>
CAN_OperatingMode_Sleep ((uint8_t)0x02)
<01>
IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) || ((MODE) == CAN_OperatingMode_Normal)|| ((MODE) == CAN_OperatingMode_Sleep))
<01>
CAN_ModeStatus_Failed ((uint8_t)0x00)
<01>
CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed)
<01>CAN_SJW_1tq ((uint8_t)0x00)
<01>CAN_SJW_2tq ((uint8_t)0x01)
<01>CAN_SJW_3tq ((uint8_t)0x02)
<01>CAN_SJW_4tq ((uint8_t)0x03)
<01>IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
<01>CAN_BS1_1tq ((uint8_t)0x00)
<01>CAN_BS1_2tq ((uint8_t)0x01)
<01>CAN_BS1_3tq ((uint8_t)0x02)
<01>CAN_BS1_4tq ((uint8_t)0x03)
<01>CAN_BS1_5tq ((uint8_t)0x04)
<01>CAN_BS1_6tq ((uint8_t)0x05)
<01>CAN_BS1_7tq ((uint8_t)0x06)
<01>CAN_BS1_8tq ((uint8_t)0x07)
<01>CAN_BS1_9tq ((uint8_t)0x08)
<01>CAN_BS1_10tq ((uint8_t)0x09)
<01>CAN_BS1_11tq ((uint8_t)0x0A)
<01>CAN_BS1_12tq ((uint8_t)0x0B)
<01>CAN_BS1_13tq ((uint8_t)0x0C)
<01>CAN_BS1_14tq ((uint8_t)0x0D)
<01>CAN_BS1_15tq ((uint8_t)0x0E)
<01>CAN_BS1_16tq ((uint8_t)0x0F)
<01>IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
<01>CAN_BS2_1tq ((uint8_t)0x00)
<01>CAN_BS2_2tq ((uint8_t)0x01)
<01>CAN_BS2_3tq ((uint8_t)0x02)
<01>CAN_BS2_4tq ((uint8_t)0x03)
<01>CAN_BS2_5tq ((uint8_t)0x04)
<01>CAN_BS2_6tq ((uint8_t)0x05)
<01>CAN_BS2_7tq ((uint8_t)0x06)
<01>CAN_BS2_8tq ((uint8_t)0x07)
<01>IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
<01>IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
<01>IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
<01>CAN_FilterMode_IdMask ((uint8_t)0x00)
<01>CAN_FilterMode_IdList ((uint8_t)0x01)
<01>IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || ((MODE) == CAN_FilterMode_IdList))
<01>CAN_FilterScale_16bit ((uint8_t)0x00)
<01>CAN_FilterScale_32bit ((uint8_t)0x01)
<01>IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || ((SCALE) == CAN_FilterScale_32bit))
<01>CAN_Filter_FIFO0 ((uint8_t)0x00)
<01>CAN_Filter_FIFO1 ((uint8_t)0x01)
<01>IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || ((FIFO) == CAN_FilterFIFO1))
<01>CAN_FilterFIFO0 CAN_Filter_FIFO0
<01>CAN_FilterFIFO1 CAN_Filter_FIFO1
<01>IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
<01>IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
<01>IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
<01>IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
<01>IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
<01>CAN_Id_Standard ((uint32_t)0x00000000)
<01>CAN_Id_Extended ((uint32_t)0x00000004)
<01>IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || ((IDTYPE) == CAN_Id_Extended))
<01>CAN_ID_STD CAN_Id_Standard
<01>CAN_ID_EXT CAN_Id_Extended
<01>CAN_RTR_Data ((uint32_t)0x00000000)
<01>CAN_RTR_Remote ((uint32_t)0x00000002)
<01>IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
<01>CAN_RTR_DATA CAN_RTR_Data
<01>CAN_RTR_REMOTE CAN_RTR_Remote
<01>CAN_TxStatus_Failed ((uint8_t)0x00)
<01>CAN_TxStatus_Ok ((uint8_t)0x01)
<01>CAN_TxStatus_Pending ((uint8_t)0x02)
<01>CAN_TxStatus_NoMailBox ((uint8_t)0x04)
<01>CANTXFAILED CAN_TxStatus_Failed
<01>CANTXOK CAN_TxStatus_Ok
<01>CANTXPENDING CAN_TxStatus_Pending
<01>CAN_NO_MB CAN_TxStatus_NoMailBox
<01>CAN_FIFO0 ((uint8_t)0x00)
<01>CAN_FIFO1 ((uint8_t)0x01)
<01>I
..\FWLIB\inc\stm32f4xx_can.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>CAN_PrescalerI
#CAN_Mode:
#CAN_SJW:
#CAN_BS1:
#CAN_BS2:
#CAN_TTCM<10>#CAN_ABOM<10>#CAN_AWUM<10>#CAN_NART<10>#	CAN_RFLM<10>#
CAN_TXFP<10>#PCAN_InitTypeDef<12>
]*<2A>CAN_FilterIdHighI
#CAN_FilterIdLowI
#CAN_FilterMaskIdHighI
#CAN_FilterMaskIdLowI
#CAN_FilterFIFOAssignmentI
#CAN_FilterNumber:
#
CAN_FilterMode:
#CAN_FilterScale:
#CAN_FilterActivation<10>#
PCAN_FilterInitTypeDef<12>

<01>
*<2A>StdIdY
#ExtIdY
#IDE:
#RTR:
#	DLC:
#
<03>:

Data#PCanTxMsg<12>
<01>
*<2A>StdIdY
#ExtIdY
#IDE:
#RTR:
#	DLC:
#
<03>:

Data~#FMI:
#PCanRxMsg5
<01>

<00><00><00>

__STM32F4xx_DAC_H &
QDAC_Trigger_None ((uint32_t)0x00000000)
SDAC_Trigger_T2_TRGO ((uint32_t)0x00000024)
TDAC_Trigger_T4_TRGO ((uint32_t)0x0000002C)
UDAC_Trigger_T5_TRGO ((uint32_t)0x0000001C)
VDAC_Trigger_T6_TRGO ((uint32_t)0x00000004)
WDAC_Trigger_T7_TRGO ((uint32_t)0x00000014)
XDAC_Trigger_T8_TRGO ((uint32_t)0x0000000C)
ZDAC_Trigger_Ext_IT9 ((uint32_t)0x00000034)
[DAC_Trigger_Software ((uint32_t)0x0000003C)
]IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || ((TRIGGER) == DAC_Trigger_T6_TRGO) || ((TRIGGER) == DAC_Trigger_T8_TRGO) || ((TRIGGER) == DAC_Trigger_T7_TRGO) || ((TRIGGER) == DAC_Trigger_T5_TRGO) || ((TRIGGER) == DAC_Trigger_T2_TRGO) || ((TRIGGER) == DAC_Trigger_T4_TRGO) || ((TRIGGER) == DAC_Trigger_Ext_IT9) || ((TRIGGER) == DAC_Trigger_Software))
oDAC_WaveGeneration_None ((uint32_t)0x00000000)
pDAC_WaveGeneration_Noise ((uint32_t)0x00000040)
qDAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
rIS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || ((WAVE) == DAC_WaveGeneration_Noise) || ((WAVE) == DAC_WaveGeneration_Triangle))
}DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000)
~DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100)
DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200)
<01>
DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300)
<01>
DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400)
<01>
DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500)
<01>
DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600)
<01>
DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700)
<01>
DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800)
<01>
DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900)
<01>
DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00)
<01>
DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00)
<01>
DAC_TriangleAmplitude_1 ((uint32_t)0x00000000)
<01>
DAC_TriangleAmplitude_3 ((uint32_t)0x00000100)
<01>
DAC_TriangleAmplitude_7 ((uint32_t)0x00000200)
<01>
DAC_TriangleAmplitude_15 ((uint32_t)0x00000300)
<01>
DAC_TriangleAmplitude_31 ((uint32_t)0x00000400)
<01>
DAC_TriangleAmplitude_63 ((uint32_t)0x00000500)
<01>
DAC_TriangleAmplitude_127 ((uint32_t)0x00000600)
<01>
DAC_TriangleAmplitude_255 ((uint32_t)0x00000700)
<01>
DAC_TriangleAmplitude_511 ((uint32_t)0x00000800)
<01>
DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900)
<01>
DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00)
<01>
DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00)
<01>
IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || ((VALUE) == DAC_LFSRUnmask_Bits1_0) || ((VALUE) == DAC_LFSRUnmask_Bits2_0) || ((VALUE) == DAC_LFSRUnmask_Bits3_0) || ((VALUE) == DAC_LFSRUnmask_Bits4_0) || ((VALUE) == DAC_LFSRUnmask_Bits5_0) || ((VALUE) == DAC_LFSRUnmask_Bits6_0) || ((VALUE) == DAC_LFSRUnmask_Bits7_0) || ((VALUE) == DAC_LFSRUnmask_Bits8_0) || ((VALUE) == DAC_LFSRUnmask_Bits9_0) || ((VALUE) == DAC_LFSRUnmask_Bits10_0) || ((VALUE) == DAC_LFSRUnmask_Bits11_0) || ((VALUE) == DAC_TriangleAmplitude_1) || ((VALUE) == DAC_TriangleAmplitude_3) || ((VALUE) == DAC_TriangleAmplitude_7) || ((VALUE) == DAC_TriangleAmplitude_15) || ((VALUE) == DAC_TriangleAmplitude_31) || ((VALUE) == DAC_TriangleAmplitude_63) || ((VALUE) == DAC_TriangleAmplitude_127) || ((VALUE) == DAC_TriangleAmplitude_255) || ((VALUE) == DAC_TriangleAmplitude_511) || ((VALUE) == DAC_TriangleAmplitude_1023) || ((VALUE) == DAC_TriangleAmplitude_2047) || ((VALUE) == DAC_TriangleAmplitude_4095))
<01>
DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
<01>
DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
<01>
IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || ((STATE) == DAC_OutputBuffer_Disable))
<01>
DAC_Channel_1 ((uint32_t)0x00000000)
<01>
DAC_Channel_2 ((uint32_t)0x00000010)
<01>
IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || ((CHANNEL) == DAC_Channel_2))
<01>
DAC_Align_12b_R ((uint32_t)0x00000000)
<01>
DAC_Align_12b_L ((uint32_t)0x00000004)
<01>
DAC_Align_8b_R ((uint32_t)0x00000008)
<01>
IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || ((ALIGN) == DAC_Align_12b_L) || ((ALIGN) == DAC_Align_8b_R))
<01>
DAC_Wave_Noise ((uint32_t)0x00000040)
<01>
DAC_Wave_Triangle ((uint32_t)0x0000
..\FWLIB\inc\stm32f4xx_dac.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>DAC_TriggerY
#DAC_WaveGenerationY
#DAC_LFSRUnmask_TriangleAmplitudeY
#DAC_OutputBufferY
#PDAC_InitTypeDef<12>
E
<00><00><00>

__STM32F4xx_DCMI_H %
rDCMI_CaptureMode_Continuous ((uint16_t)0x0000)
tDCMI_CaptureMode_SnapShot ((uint16_t)0x0002)
vIS_DCMI_CAPTURE_MODE(MODE) (((MODE) == DCMI_CaptureMode_Continuous) || ((MODE) == DCMI_CaptureMode_SnapShot))
<01>
DCMI_SynchroMode_Hardware ((uint16_t)0x0000)
<01>
DCMI_SynchroMode_Embedded ((uint16_t)0x0010)
<01>
IS_DCMI_SYNCHRO(MODE) (((MODE) == DCMI_SynchroMode_Hardware) || ((MODE) == DCMI_SynchroMode_Embedded))
<01>
DCMI_PCKPolarity_Falling ((uint16_t)0x0000)
<01>
DCMI_PCKPolarity_Rising ((uint16_t)0x0020)
<01>
IS_DCMI_PCKPOLARITY(POLARITY) (((POLARITY) == DCMI_PCKPolarity_Falling) || ((POLARITY) == DCMI_PCKPolarity_Rising))
<01>
DCMI_VSPolarity_Low ((uint16_t)0x0000)
<01>
DCMI_VSPolarity_High ((uint16_t)0x0080)
<01>
IS_DCMI_VSPOLARITY(POLARITY) (((POLARITY) == DCMI_VSPolarity_Low) || ((POLARITY) == DCMI_VSPolarity_High))
<01>
DCMI_HSPolarity_Low ((uint16_t)0x0000)
<01>
DCMI_HSPolarity_High ((uint16_t)0x0040)
<01>
IS_DCMI_HSPOLARITY(POLARITY) (((POLARITY) == DCMI_HSPolarity_Low) || ((POLARITY) == DCMI_HSPolarity_High))
<01>
DCMI_CaptureRate_All_Frame ((uint16_t)0x0000)
<01>
DCMI_CaptureRate_1of2_Frame ((uint16_t)0x0100)
<01>
DCMI_CaptureRate_1of4_Frame ((uint16_t)0x0200)
<01>
IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || ((RATE) == DCMI_CaptureRate_1of2_Frame) || ((RATE) == DCMI_CaptureRate_1of4_Frame))
<01>
DCMI_ExtendedDataMode_8b ((uint16_t)0x0000)
<01>
DCMI_ExtendedDataMode_10b ((uint16_t)0x0400)
<01>
DCMI_ExtendedDataMode_12b ((uint16_t)0x0800)
<01>
DCMI_ExtendedDataMode_14b ((uint16_t)0x0C00)
<01>
IS_DCMI_EXTENDED_DATA(DATA) (((DATA) == DCMI_ExtendedDataMode_8b) || ((DATA) == DCMI_ExtendedDataMode_10b) || ((DATA) == DCMI_ExtendedDataMode_12b) || ((DATA) == DCMI_ExtendedDataMode_14b))
<01>
DCMI_IT_FRAME ((uint16_t)0x0001)
<01>
DCMI_IT_OVF ((uint16_t)0x0002)
<01>
DCMI_IT_ERR ((uint16_t)0x0004)
<01>
DCMI_IT_VSYNC ((uint16_t)0x0008)
<01>
DCMI_IT_LINE ((uint16_t)0x0010)
<01>
IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
<01>
IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || ((IT) == DCMI_IT_OVF) || ((IT) == DCMI_IT_ERR) || ((IT) == DCMI_IT_VSYNC) || ((IT) == DCMI_IT_LINE))
<01>
DCMI_FLAG_HSYNC ((uint16_t)0x2001)
<01>
DCMI_FLAG_VSYNC ((uint16_t)0x2002)
<01>
DCMI_FLAG_FNE ((uint16_t)0x2004)
<01>
DCMI_FLAG_FRAMERI ((uint16_t)0x0001)
<01>
DCMI_FLAG_OVFRI ((uint16_t)0x0002)
<01>
DCMI_FLAG_ERRRI ((uint16_t)0x0004)
<01>
DCMI_FLAG_VSYNCRI ((uint16_t)0x0008)
<01>
DCMI_FLAG_LINERI ((uint16_t)0x0010)
<01>
DCMI_FLAG_FRAMEMI ((uint16_t)0x1001)
<01>
DCMI_FLAG_OVFMI ((uint16_t)0x1002)
<01>
DCMI_FLAG_ERRMI ((uint16_t)0x1004)
<01>
DCMI_FLAG_VSYNCMI ((uint16_t)0x1008)
<01>
DCMI_FLAG_LINEMI ((uint16_t)0x1010)
<01>
IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || ((FLAG) == DCMI_FLAG_VSYNC) || ((FLAG) == DCMI_FLAG_FNE) || ((FLAG) == DCMI_FLAG_FRAMERI) || ((FLAG) == DCMI_FLAG_OVFRI) || ((FLAG) == DCMI_FLAG_ERRRI) || ((FLAG) == DCMI_FLAG_VSYNCRI) || ((FLAG) == DCMI_FLAG_LINERI) || ((FLAG) == DCMI_FLAG_FRAMEMI) || ((FLAG) == DCMI_FLAG_OVFMI) || ((FLAG) == DCMI_FLAG_ERRMI) || ((FLAG) == DCMI_FLAG_VSYNCMI) || ((FLAG) == DCMI_FLAG_LINEMI))
<01>IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))XM






..\FWLIB\inc\..\USER\stm32f4xx_dcmi.h
stm32f4xx.h

<01>
..\FWLIB\inc\stm32f4xx_dcmi.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>DCMI_CaptureModeI
#DCMI_SynchroModeI
#DCMI_PCKPolarityI
#DCMI_VSPolarityI
#DCMI_HSPolarityI
#DCMI_CaptureRateI
#
DCMI_ExtendedDataModeI
#PDCMI_InitTypeDef<12>
I*<2A>DCMI_VerticalStartLineI
#DCMI_HorizontalOffsetCountI
#DCMI_VerticalLineCountI
#DCMI_CaptureCountI
#PDCMI_CROPInitTypeDef<12>

\*<2A>DCMI_FrameStartCode:
#DCMI_LineStartCode:
#
DCMI_LineEndCode:
#DCMI_FrameEndCode:
#PDCMI_CodesInitTypeDef:
g
<00><00><00>

__STM32F4xx_FSMC_H &
<01>
FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
<01>
FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
<01>
FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
<01>
FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
<01>FSMC_Bank2_NAND ((uint32_t)0x00000010)
<01>FSMC_Bank3_NAND ((uint32_t)0x00000100)
<01>FSMC_Bank4_PCCARD ((uint32_t)0x00001000)
<01>IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || ((BANK) == FSMC_Bank1_NORSRAM2) || ((BANK) == FSMC_Bank1_NORSRAM3) || ((BANK) == FSMC_Bank1_NORSRAM4))
<01>IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND))
<01>IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND) || ((BANK) == FSMC_Bank4_PCCARD))
<01>IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || ((BANK) == FSMC_Bank3_NAND) || ((BANK) == FSMC_Bank4_PCCARD))
<01>FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
<01>FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
<01>IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || ((MUX) == FSMC_DataAddressMux_Enable))
<01>FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
<01>FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
<01>FSMC_MemoryType_NOR ((uint32_t)0x00000008)
<01>IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || ((MEMORY) == FSMC_MemoryType_PSRAM)|| ((MEMORY) == FSMC_MemoryType_NOR))
<01>FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
<01>FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
<01>IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || ((WIDTH) == FSMC_MemoryDataWidth_16b))
<01>FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
<01>FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
<01>IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || ((STATE) == FSMC_BurstAccessMode_Enable))
<01>FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
<01>FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
<01>IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || ((STATE) == FSMC_AsynchronousWait_Enable))
<01>FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
<01>FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
<01>IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || ((POLARITY) == FSMC_WaitSignalPolarity_High))
<01>FSMC_WrapMode_Disable ((uint32_t)0x00000000)
<01>FSMC_WrapMode_Enable ((uint32_t)0x00000400)
<01>IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || ((MODE) == FSMC_WrapMode_Enable))
<01>FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
<01>FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
<01>IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
<01>FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
<01>FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
<01>IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || ((OPERATION) == FSMC_WriteOperation_Enable))
<01>FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
<01>FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
<01>IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || ((SIGNAL) == FSMC_WaitSignal_Enable))
<01>FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
<01>FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
<01>IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || ((MODE) == FSMC_ExtendedMode_Enable))
<01>FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
<01>FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
<01>IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || ((BURST) == FSMC_WriteBurst_Enable))
<01>IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
<01>IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
<01>IS_FSMC_DATASETUP_TIME(TIME) (((TIME) >
..\FWLIB\inc\stm32f4xx_fsmc.hComponent: ARM Compiler 5.06 update 6 (build 750) Tool: ArmCC [4d3637]C:\Users\zdw\Desktop\stm32f407_ZNKT01_09.1(1)\stm32f407_ZNKT01_09.1\USER*<2A>FSMC_AddressSetupTimeY
#FSMC_AddressHoldTimeY
#FSMC_DataSetupTimeY
#FSMC_BusTurnAroundDurationY
#FSMC_CLKDivisionY
#FSMC_DataLatencyY
#FSMC_AccessModeY
#PFSMC_NORSRAMTimingInitTypeDef<12>
Y*<2A><FSMC_BankY
#FSMC_DataAddressMuxY
#FSMC_MemoryTypeY
#FSMC_MemoryDataWidthY
#FSMC_BurstAccessModeY
#FSMC_AsynchronousWaitY
#FSMC_WaitSignalPolarityY
#FSMC_WrapModeY
#FSMC_WaitSignalActiveY
# FSMC_WriteOperationY
#$FSMC_WaitSignalY
#(FSMC_ExtendedModeY
#,FSMC_WriteBurstY
#0FSMC_ReadWriteTimingStructb#4FSMC_WriteTimingStructb#8"<12>
PFSMC_NORSRAMInitTypeDef<12>

<01>
*<2A>FSMC_SetupTimeY
#FSMC_WaitSetupTimeY
#FSMC_HoldSetupTimeY
#FSMC_HiZSetupTimeY
#PFSMC_NAND_PCCARDTimingInitTypeDef<12>
<01>
*<2A>
$FSMC_BankY
#FSMC_WaitfeatureY
#FSMC_MemoryDataWidthY
#FSMC_ECCY
#FSMC_ECCPageSizeY
#FSMC_TCLRSetupTimeY
#FSMC_TARSetupTimeY
#FSMC_CommonSpaceTimingStruct#FSMC_AttributeSpaceTimingStruct# "<12>PFSMC_NANDInitTypeDef 
<01>
*<2A>FSMC_WaitfeatureY
#FSMC_TCLRSetupTimeY
#FSMC_TARSetupTimeY
#FSMC_CommonSpaceTimingStruct#FSMC_AttributeSpaceTimingStruct#FSMC_IOSpaceTimingStruct#PFSMC_PCCARDInitTypeDef?
<01>

<00><00><00>

__STM32F4xx_CONF_H "#$%&'()	*
+,-
./01234PQRSTUV
xassert_param(expr) ((void)0)@6






..\USER\..\FWLIB\inc\stm32f4xx_conf.h
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